From patchwork Fri Jun 3 21:26:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9154089 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 33C616082E for ; Fri, 3 Jun 2016 21:28:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 24540282EE for ; Fri, 3 Jun 2016 21:28:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 194E328338; Fri, 3 Jun 2016 21:28:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ADA52282EE for ; Fri, 3 Jun 2016 21:27:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b8wc1-0004Lc-VY; Fri, 03 Jun 2016 21:26:37 +0000 Received: from mail-lf0-x22d.google.com ([2a00:1450:4010:c07::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b8wbz-0004Ha-8f for linux-arm-kernel@lists.infradead.org; Fri, 03 Jun 2016 21:26:36 +0000 Received: by mail-lf0-x22d.google.com with SMTP id b73so62220675lfb.3 for ; Fri, 03 Jun 2016 14:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:organization:user-agent :in-reply-to:references:mime-version:content-transfer-encoding; bh=npgTnJPDxLsFIv9Ul3QM1CdmOcbBwA0JUOcB5x6KJX8=; b=WRHEC+rlPjagG6fzql9Cu5NAExPAPQph3JN7iOCPMnI/FzR6BwSYHWoKisjURlcysl AT0tLSFuAqRXeIw3TAAhJN3XzQXeBJwyGxaHXr+padxniq/YokKwYK4cMYwTITAqGmEz m6psOnUJhAk3cVB38YG9FRM/+uibQzZO3O/+XdyEFbP4g5WzvRwURE5Ivb3sBV66WyxO pEULvKhGq26Oct+M48Vt1d8Sb4uY1vRQZ2/v9VA+gswGMWgFSiHGDL5+eIMog4V8jumx hNHp8SnKi4UZSQkucapE+F88ynYerorFpP5et1pGlHvVHsO6kzjPCd5lA0WoCpM2a6vf Mx9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding; bh=npgTnJPDxLsFIv9Ul3QM1CdmOcbBwA0JUOcB5x6KJX8=; b=h1p4o9zCKdRCSq7jVG4hzDnDqQiJW7EERCjWd6EHlM0RCf2NahmBBZypIY3SOy7ykt l/qr23GETekBkhXBdW40iHXnH83dpp2bpyVpdZtYWwZdH8LO1/zcA/GDjCxUc30CI03s jEbKFy1Jp6SZa7ghS/BXm5i2/xQudfd7Cb/uWxMnFwbJHidPunvcZXOAQxLvjJeV4nAU BeYlLLd+qhYNjXyMeHajFBnMNao2GvFmBsKBT6th3+Fz0rcvpnhXWL0IQhImVf4GF4Sj 90d1d50FThD+SCIurF0LIPOf+0gZMskUd4tgQ/B/wo14DPam9NmjeUqxoR+VIGCKbPyk sExA== X-Gm-Message-State: ALyK8tL1FRk218FId5CzHlVg34EZBNYWsHpd5BLdxCTfVzuJSvE4+Eby08hsPTO2DueB/A== X-Received: by 10.25.162.130 with SMTP id l124mr1830059lfe.175.1464989173338; Fri, 03 Jun 2016 14:26:13 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.86.122]) by smtp.gmail.com with ESMTPSA id 95sm556091ljb.13.2016.06.03.14.26.11 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Jun 2016 14:26:12 -0700 (PDT) From: Sergei Shtylyov To: horms@verge.net.au, linux-renesas-soc@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org Subject: [PATCH v2 05/11] ARM: dts: r8a7792: initial SoC device tree Date: Sat, 04 Jun 2016 00:26:10 +0300 Message-ID: <2268000.l71DRbJSRE@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.10 (Linux/4.4.11-200.fc22.x86_64; KDE/4.14.17; x86_64; ; ) In-Reply-To: <3446154.oZ24315zaL@wasted.cogentembedded.com> References: <3446154.oZ24315zaL@wasted.cogentembedded.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160603_142635_674451_7E92DFDA X-CRM114-Status: GOOD ( 12.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux@arm.linux.org.uk, magnus.damm@gmail.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The initial R8A7792 SoC device tree including CPU core, GIC, timer, SYSC, and the required clock descriptions. Signed-off-by: Sergei Shtylyov --- Changes in version 2: - explicitly included the IRQ header; - removed the CPU1 node; - removed the audio and PCIe bus clocks; - removed the SDH, SD0, and SD1 CPG clocks; - added RCAN and ADSP CPG clocks; - removed the PLL1/2, Z2, ZS, I, B, P, CL, M2, RCLK, OSCCLK, ZB3, ZB3D2, DDR, and MP fixed factor clocks; - fixed up the parent and divisor for the CP fixed factor clock; - swapped the SYS-DMAC0/1 clocks; - removed all gated clocks except the [H]SCIF, IRQC, and SYS-DMAC ones; - created the "soc" subnode, moving the SoC device nodes there; - removed the "clocks" node, moving its fixed clock subnodes to the root and the MSTP subnodes into the "soc" node. arch/arm/boot/dts/r8a7792.dtsi | 171 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7792.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7792.dtsi @@ -0,0 +1,171 @@ +/* + * Device Tree Source for the r8a7792 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7792"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7792_CLK_Z>; + power-domains = <&sysc R8A7792_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7792_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7792-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7792-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "z", "rcan", "adsp"; + #power-domain-cells = <0>; + }; + + /* Gate clocks */ + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 + >; + clock-output-names = "sys-dmac1", "sys-dmac0"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "irqc"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 + R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 + R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 + >; + clock-output-names = "hscif1", "hscif0", "scif3", + "scif2", "scif1", "scif0", + "du1", "du0"; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* Fixed factor clocks */ + zs_clk: zs { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + p_clk: p { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + }; +};