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Fri, 10 Jan 2025 19:32:49 -0800 From: Nicolin Chen To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv2 02/13] genirq/msi: Rename iommu_dma_compose_msi_msg() to msi_msg_set_msi_addr() Date: Fri, 10 Jan 2025 19:32:18 -0800 Message-ID: <242034456c0bfcd7ecf75cb29d8e5c99db0675d6.1736550979.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|DM4PR12MB6279:EE_ X-MS-Office365-Filtering-Correlation-Id: 229d0163-a0d3-4d97-53de-08dd31f0a186 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: PrOtRRaXbwLyEfxBH44VbUhqWRxIQMYi+Mtd5AyyejoJty/VSjeCPaZmCOBkT5XvtJbe4O9Wbct5QI+Lig6owbA2JsITITUkKkDRBwkggKWouMsVWDdsz0h5uCsMq1GKDMmbQ4/cxhha5ozmmoRySMwtB1ixJcsPzCExlnxCvn56MX2kGv3VUyAAaFe3ja3NNNYoZI8e70Q9RhbLJ6vS5NAmFghARUO9rWjx7dQHfQv0KS+Q8ViJAfmAkGDli0XKsGriFqy5sxYeDCK72kG5fLKdUzXvkh/82wYBl4YdqlKkmVav6K7yzO5bOnhv8dcGuaOaLxIDZpm2gOACOudGZHfeibiQei/mJyV8hIbGYc02DebUuKVHoQW7qDcVr+zSg8cM5HqdqZumBedZ+GQDJBFd7ulMEN7tpwuWmXDAcyOAH0jvTuJ4d8QTbQNv4BdYfahBzYkPbdT+un9IA2Dv5Fd5reTtGp4+5xtQqLKDHSsbBB199lYH9dOBrW1Gu99McArmQG/jfvuMyM1ai/xTs5drfEyNTAMJbdwxPApLm7INaLxVwd/bDarHU8la2gAcRZxDFqvrIIx6pQFa7UBG6poedTLsoDxha3VORhWkt5m9fBPUn5E4JL7zqzZijvQgWnAgNF5IFFMI8ZJ926sxaTPsl/Dw8g48hM39NNkQOwUDXm06rhhTReeE8V6euQbEWbEorZCbZT8tizJFwRYKyevTEGNq5Ys+bncS9NB5U9icT8qDYuG5gx6GAnOKHcB8A6SDNEyraxzzJku/sRtYpKizzq1Uqknwy/ZgXP1rnh2BczN/5yV99bqAw6nfQ80sI86kYiCePJj941bWfytr7fDEPhI9+dVDD9B6XqL9FOIfDDoFOvtpAFwu3niQTH16JaGVK4ZTkpon2sY8ptzv0TQXq7SkSM8qOdZwQ4brC78MXTe9n/nAasXM5sOzVToSAFG5cdvw7tXTLBhqhX90UpjtNAVle8/gMO9FAsfNgaRXTdykAVNsz0Qaw/voqtwdiQBCbPtMRr18rrErkXZ57jTyr+t8LWN0laiB89rIbSvI/a3cmm9jEVsctp4vPetMAJ53M5muWdxP1HJcLpjbt3lWwXCgdxUBrsw+O4JhpDFck6MCXdalH38lHAxyXq10CMsJ5QFu4ZnEbwTBKpq4JrCUcEXiKhDxBeueAGgU1dCvMwiVHp6Pz4Jh8DXPs5TojkxEZlRKNW2ON0f2YmpsdlMG0f7GenmpLc38PSkhX+MlUdzTVsNCpsci5XYL0Cm86UobrX2AlMqxjuNQY/QOn+e1uLTd60nqGRmja7U4mK67vPJ8zJ/NemZ7tIy+XrJiNFvMA+CMCSILwsxqrgN5r/GzV53HVgzVg5aBvE79uou/a/qEaIvIgv3EkXzD55TqLy15ogHZS0dLgNJqNX5ql99yAWjJh922pF3tj7gAFey7znj7SYBcovZ0VvdLZm1wwcAjTBNFKWeezVCbU7IvmltsQbSX9JWiiNYUB1EfYGA= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2025 03:32:52.7075 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 229d0163-a0d3-4d97-53de-08dd31f0a186 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6279 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250110_193300_594694_76B0B00D X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jason Gunthorpe The new function is used to take in a u64 MSI address and store it in the msi_msg. If the iommu has provided an alternative address then that is replaced instead. All callers have a tidy u64 already so this also consolidates the repeated low/high code into a small helper. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/msi.h | 18 ++++++++---------- drivers/irqchip/irq-gic-v2m.c | 5 +---- drivers/irqchip/irq-gic-v3-its.c | 13 +++---------- drivers/irqchip/irq-gic-v3-mbi.c | 12 ++++-------- drivers/irqchip/irq-ls-scfg-msi.c | 5 ++--- 5 files changed, 18 insertions(+), 35 deletions(-) diff --git a/include/linux/msi.h b/include/linux/msi.h index d442b4a69d56..f6369748fc6e 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -296,13 +296,8 @@ static inline void msi_desc_set_iommu_msi_iova(struct msi_desc *desc, #endif } -/** - * iommu_dma_compose_msi_msg() - Apply translation to an MSI message - * @desc: MSI descriptor prepared by iommu_dma_prepare_msi() - * @msg: MSI message containing target physical address - */ -static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, - struct msi_msg *msg) +static inline void msi_msg_set_msi_addr(struct msi_desc *desc, + struct msi_msg *msg, u64 msi_addr) { #ifdef CONFIG_IRQ_MSI_IOMMU if (desc->iommu_msi_page_shift) { @@ -310,11 +305,14 @@ static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, << desc->iommu_msi_page_shift; msg->address_hi = upper_32_bits(msi_iova); - msg->address_lo = lower_32_bits(msi_iova) | - (msg->address_lo & - ((1 << desc->iommu_msi_page_shift) - 1)); + msg->address_lo = + lower_32_bits(msi_iova) | + (msi_addr & ((1 << desc->iommu_msi_page_shift) - 1)); + return; } #endif + msg->address_hi = upper_32_bits(msi_addr); + msg->address_lo = lower_32_bits(msi_addr); } int msi_domain_insert_msi_desc(struct device *dev, unsigned int domid, diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index be35c5349986..6599c56873ad 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -87,9 +87,6 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) struct v2m_data *v2m = irq_data_get_irq_chip_data(data); phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq); - msg->address_hi = upper_32_bits(addr); - msg->address_lo = lower_32_bits(addr); - if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) msg->data = 0; else @@ -97,7 +94,7 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) msg->data -= v2m->spi_offset; - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); + msi_msg_set_msi_addr(irq_data_get_msi_desc(data), msg, addr); } static struct irq_chip gicv2m_irq_chip = { diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 92244cfa0464..8c3ab7b471ca 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1809,17 +1809,10 @@ static u64 its_irq_get_msi_base(struct its_device *its_dev) static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); - struct its_node *its; - u64 addr; - - its = its_dev->its; - addr = its->get_msi_base(its_dev); - - msg->address_lo = lower_32_bits(addr); - msg->address_hi = upper_32_bits(addr); - msg->data = its_get_event_id(d); - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); + msg->data = its_get_event_id(d); + msi_msg_set_msi_addr(irq_data_get_msi_desc(d), msg, + its_dev->its->get_msi_base(its_dev)); } static int its_irq_set_irqchip_state(struct irq_data *d, diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c index 3fe870f8ee17..513479da9ee3 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -147,22 +147,18 @@ static const struct irq_domain_ops mbi_domain_ops = { static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR); - msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); msg[0].data = data->parent_data->hwirq; - - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); + msi_msg_set_msi_addr(irq_data_get_msi_desc(data), &msg[0], + mbi_phys_base + GICD_SETSPI_NSR); } static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg) { mbi_compose_msi_msg(data, msg); - msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); - msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); msg[1].data = data->parent_data->hwirq; - - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]); + msi_msg_set_msi_addr(irq_data_get_msi_desc(data), &msg[1], + mbi_phys_base + GICD_CLRSPI_NSR); } static bool mbi_init_dev_msi_info(struct device *dev, struct irq_domain *domain, diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c index c0e1aafe468c..2ac6d89b4cb4 100644 --- a/drivers/irqchip/irq-ls-scfg-msi.c +++ b/drivers/irqchip/irq-ls-scfg-msi.c @@ -87,8 +87,6 @@ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) { struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data); - msg->address_hi = upper_32_bits(msi_data->msiir_addr); - msg->address_lo = lower_32_bits(msi_data->msiir_addr); msg->data = data->hwirq; if (msi_affinity_flag) { @@ -98,7 +96,8 @@ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) msg->data |= cpumask_first(mask); } - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); + msi_msg_set_msi_addr(irq_data_get_msi_desc(data), msg, + msi_data->msiir_addr); } static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,