From patchwork Fri Jul 29 16:07:38 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 1021362 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6TG7t6n009779 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 29 Jul 2011 16:08:16 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QmpbE-0008Nt-Mt; Fri, 29 Jul 2011 16:07:44 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QmpbE-0005f4-6U; Fri, 29 Jul 2011 16:07:44 +0000 Received: from mail-fx0-f49.google.com ([209.85.161.49]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QmpbB-0005el-6E for linux-arm-kernel@lists.infradead.org; Fri, 29 Jul 2011 16:07:41 +0000 Received: by fxd20 with SMTP id 20so3143485fxd.36 for ; Fri, 29 Jul 2011 09:07:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:user-agent:in-reply-to :references:mime-version:content-transfer-encoding:content-type; bh=UWsYZvOavhQnQl/lyZs8CUpgafSWJJUVjnDLmJ9do9M=; b=tOwxv756Yx/q9lfEUjoJwAkfruoYLGLNBolEKfs3SQGULSZNfODJQ6KSONuF1W2vDK hYXwb87i7B+uo3gw3h3gZ5zolhWkKmdbbnnThqnaPBKLYv/8XDVzBiANP/fJY3SnS8qa 9gjxoYmo3KScGwoi3d7aBNCsNOTQyR+qQQ3Qk= Received: by 10.223.96.13 with SMTP id f13mr2051362fan.37.1311955658701; Fri, 29 Jul 2011 09:07:38 -0700 (PDT) Received: from flatron.localnet (178-73-0-134.home.aster.pl [178.73.0.134]) by mx.google.com with ESMTPS id j19sm1174074faa.17.2011.07.29.09.07.36 (version=SSLv3 cipher=OTHER); Fri, 29 Jul 2011 09:07:37 -0700 (PDT) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] ARM: s3c64xx: Add support for synchronous clock operation. Date: Fri, 29 Jul 2011 18:07:38 +0200 Message-ID: <2519722.fCRLnU1LzW@flatron> User-Agent: KMail/4.7.0 (Linux/3.0.0-gentoo; KDE/4.7.0; x86_64; ; ) In-Reply-To: <5661373.tZL1ZnPyVO@flatron> References: <5661373.tZL1ZnPyVO@flatron> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110729_120741_390109_8448BB88 X-CRM114-Status: GOOD ( 14.24 ) X-Spam-Score: -0.8 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.161.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (tomasz.figa[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 T_TO_NO_BRKTS_FREEMAIL To: misformatted and free email service Cc: Kukjin Kim , Ben Dooks X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 29 Jul 2011 16:08:16 +0000 (UTC) From c985e14a4fc5c7970d7f6c2fde6d214217214688 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 28 Jul 2011 14:34:51 +0200 Subject: [PATCH 5/5] ARM: s3c64xx: Add support for synchronous clock operation. Some boards based on S3C6410 use synchronous clocking, which means that HCLKx2 and other system clocks are generated from APLL instead of MPLL. This patch adds support for such boards, by calculating hclk2 depending on the status of S3C_OTHERS_SYNCMUXSEL_SYNC bit in S3C_OTHERS registers. --- arch/arm/mach-s3c64xx/clock.c | 8 +++++++- arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 4 ++++ 2 files changed, 11 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index fdfc4d5..56421ab 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -780,7 +780,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", apll, mpll, epll); - hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + if(__raw_readl(S3C_OTHERS) & S3C_OTHERS_SYNCMUXSEL_SYNC) + /* Synchronous mode */ + hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + else + /* Asynchronous mode */ + hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 05332b9..ac2202f 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -35,6 +35,7 @@ #define S3C_MEM0_GATE S3C_CLKREG(0x3C) #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) #define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) +#define S3C_OTHERS S3C_CLKREG(0x900) /* CLKDIV0 */ #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) @@ -159,4 +160,7 @@ #define MEM_SYS_CFG_INDEP_CF 0x4000 #define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 +/* OTHERS */ +#define S3C_OTHERS_SYNCMUXSEL_SYNC (1<<6) + #endif /* _PLAT_REGS_CLOCK_H */