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Thu, 31 May 2018 13:26:50 -0700 (PDT) Subject: [PATCH v2 2/2] arm64: dts: renesas: condor: add I2C0 support From: Sergei Shtylyov To: Simon Horman , Rob Herring , Catalin Marinas , Will Deacon , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org References: <2a88f4e9-0a86-8e6f-0ef2-20913dc9431d@cogentembedded.com> Organization: Cogent Embedded Message-ID: <2ea2c8bc-2abd-57fa-9c13-2ff55b41e0d4@cogentembedded.com> Date: Thu, 31 May 2018 23:26:49 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <2a88f4e9-0a86-8e6f-0ef2-20913dc9431d@cogentembedded.com> Content-Language: en-MW X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180531_132704_119866_C5D885A1 X-CRM114-Status: GOOD ( 16.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Magnus Damm , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Define the Condor board dependent part of the I2C0 device node. The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders and Analog Devices ADV7511W HDMI transmitter (but we're only describing the former chips now). Signed-off-by: Sergei Shtylyov Reviewed-by: Simon Horman --- Changes in version 2: - added Simon's tag. arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -80,6 +80,28 @@ clock-frequency = <32768>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander0: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander1: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &mmc0 { pinctrl-0 = <&mmc_pins>; pinctrl-1 = <&mmc_pins_uhs>; @@ -104,6 +126,11 @@ function = "canfd0"; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc";