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Thu, 15 Aug 2024 17:55:45 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v12 08/10] iommu/arm-smmu-v3: Add struct arm_smmu_impl_ops Date: Thu, 15 Aug 2024 17:55:29 -0700 Message-ID: <2f9f677df068557e8cc399406eeed2d1926e41d6.1723754745.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F3:EE_|CY8PR12MB8065:EE_ X-MS-Office365-Filtering-Correlation-Id: a66e9156-77ba-40e8-fe62-08dcbd8e3358 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: OSCmAp4E5ujGFZug/HR5mb8CGhR7XQe5iDAZcHVjWKvjJn1B0v7vg1k7emd7vkMhlvEt+UIDRV5TABT+c718on24o8G8hUE6vFUJulJocSu01L33cnIJJEeNfsPal/R1rz0OBY/kmitRzb8LJClRqhdXmSBUR7lvzBT3DsSkGHjH8Aizw4TV8rJErp6QOvTYeZWoolRto39tpm/wO4RGwTkJDkfmkgbMXXIlpnBgHiUKeOm+3NATLC4sWNJN/qWyU8kDVz77e8UoT7AwAHkpXB5qwNPjDQkhazShkG1SbR54gwjqoeZMuEkVzTi4z8JXrvH5LYGmdatmSRYQhby++YwLl6Og8D+/AgDGeFisvK+h3nhMd3XkjJUe2Qj4hj/gJ0hNCcVe6a8IpIS3KFIJVB+FlkrTCpGZs/mfavAcFTIrjepJPq4I4gQu2DSSz9n2dvLz2p9flbYY8IQxjCGIsGQopN+ss2iQ+bXMJyS8EMbE5NBXdt668iAy2alnvPsthDoyd00OEVrxu2Z3AZY10rTOP0RLj8t1nMTwYY78a314ZTP99GUU1ugs08cwvsFWqjWrTLomXzpTMbL7W6rLtcKkC57uGsIwZfJmtw6jIu5DR0ck3+5xXILwPGEEI1pLJFwcm7MgaQ/TZx1BSozX6LSFBPL/Cm81M/Y/Xmj79EmrJI2ERRnyod1GySWSs8RiwSm5mYvpGQL9zUx3hyud7NQ4M4RSd2FO7ThQu9XwwqDWHE8zYapdnbKypcaX6KwtPefsyC/zYUHkV6YVDyXZaZWfL5FXKrpQZYVk6uc9dSVTIHwncjbZk1g1d0P6MaccAGmWZuYnzi2wlLH5qfeHACQJdb1aD/It/r0CjubIZP+KqIrMKS2i0o9hncZJ/+nFvSn2ObJ/tHOfuCNvsZh5sg/VvwMM750UWX2dcg6J4QJ6f1yexQE67LwjpwmcUKYf/P5VF3YtFaAG5WEe8iUuQkzVBzHBm1qqFgwqFdJ3gMQ5wogtGc+p3IqxQqyOVZNaSESaoSt6WyFyn/+CAdOXwI8uupFsKMaJQQh8qaD4dOvmy32Xmu8GEAB6/ABOst/w8LYYOeo6gG3A22V+K4udM58HHsFLlNP4ilnAsjXurkyGlneItdnt2M6ZBMUXF7/f/npd2DVvMq9mvQoCUQkvcGSCbM1z1SzRKIHErdALmWlk23MqSE/YLhtoxxZUlaivE/BXtOajQhzvPTPfiWB4BUXfB6kzFNcPxG/j5Zy/+t6t3qzFxe4YF70BHJ4yO1cSDqg+UBlg+Vg3gnAk4FU6I2w2VaqEH24U5PJh2erXOGAhV3CpOjiJIBF7Q4EkHpjMWimHgqny/OBnktssRyEPP1axl7r95jH5rG3eG3ekCpmchXAiSjuIxKUyZKrz61BVn4l2NLao/yGYMePnYBtrmtLR7QdYtMTBOO6SBdW19VIOfQdmPeK4YE9WnGpi8GGs X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 00:56:02.3306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a66e9156-77ba-40e8-fe62-08dcbd8e3358 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8065 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_175609_871674_ECF890F1 X-CRM114-Status: GOOD ( 19.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jason Gunthorpe NVIDIA Tegra241 implemented SMMU in a slightly different way that supports a CMDQV extension feature as a secondary CMDQ for virtualization cases. Mimicing the arm-smmu (v2) driver, introduce a struct arm_smmu_impl_ops to accommodate impl routines. Suggested-by: Will Deacon Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 51 ++++++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 ++++ 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6df3cb0bc406..2159455cd781 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -338,7 +338,12 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) { - return &smmu->cmdq; + struct arm_smmu_cmdq *cmdq = NULL; + + if (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq) + cmdq = smmu->impl_ops->get_secondary_cmdq(smmu); + + return cmdq ?: &smmu->cmdq; } static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, @@ -4044,6 +4049,14 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } + if (smmu->impl_ops && smmu->impl_ops->device_reset) { + ret = smmu->impl_ops->device_reset(smmu); + if (ret) { + dev_err(smmu->dev, "failed to reset impl\n"); + return ret; + } + } + return 0; } @@ -4450,6 +4463,38 @@ static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); } +static void arm_smmu_impl_remove(void *data) +{ + struct arm_smmu_device *smmu = data; + + if (smmu->impl_ops && smmu->impl_ops->device_remove) + smmu->impl_ops->device_remove(smmu); +} + +/* + * Probe all the compiled in implementations. Each one checks to see if it + * matches this HW and if so returns a devm_krealloc'd arm_smmu_device which + * replaces the callers. Otherwise the original is returned or ERR_PTR. + */ +static struct arm_smmu_device *arm_smmu_impl_probe(struct arm_smmu_device *smmu) +{ + struct arm_smmu_device *new_smmu = ERR_PTR(-ENODEV); + int ret; + + /* Add impl probe */ + + if (new_smmu == ERR_PTR(-ENODEV)) + return smmu; + if (IS_ERR(new_smmu)) + return new_smmu; + + ret = devm_add_action_or_reset(new_smmu->dev, arm_smmu_impl_remove, + new_smmu); + if (ret) + return ERR_PTR(ret); + return new_smmu; +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -4471,6 +4516,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (ret) return ret; + smmu = arm_smmu_impl_probe(smmu); + if (IS_ERR(smmu)) + return PTR_ERR(smmu); + /* Base address */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 9f5d156b73af..475517729307 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -15,6 +15,7 @@ #include struct acpi_iort_node; +struct arm_smmu_device; /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 @@ -629,9 +630,17 @@ struct arm_smmu_strtab_cfg { u32 strtab_base_cfg; }; +struct arm_smmu_impl_ops { + int (*device_reset)(struct arm_smmu_device *smmu); + void (*device_remove)(struct arm_smmu_device *smmu); + struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu); +}; + /* An SMMUv3 instance */ struct arm_smmu_device { struct device *dev; + const struct arm_smmu_impl_ops *impl_ops; + void __iomem *base; void __iomem *page1;