From patchwork Wed Feb 10 12:41:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Persson X-Patchwork-Id: 8270821 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0300FBEEE5 for ; Wed, 10 Feb 2016 12:45:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0DBA82039C for ; Wed, 10 Feb 2016 12:45:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 24B7520396 for ; Wed, 10 Feb 2016 12:45:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTU7S-00055M-2B; Wed, 10 Feb 2016 12:43:42 +0000 Received: from bastet.se.axis.com ([195.60.68.11]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTU6f-0004kq-U0 for linux-arm-kernel@lists.infradead.org; Wed, 10 Feb 2016 12:42:57 +0000 Received: from localhost (localhost [127.0.0.1]) by bastet.se.axis.com (Postfix) with ESMTP id 7A70D18125; Wed, 10 Feb 2016 13:42:33 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at bastet.se.axis.com X-Amavis-Alert: BAD HEADER SECTION, Duplicate header field: "References" Received: from bastet.se.axis.com ([IPv6:::ffff:127.0.0.1]) by localhost (bastet.se.axis.com [::ffff:127.0.0.1]) (amavisd-new, port 10024) with LMTP id fn0tz8+r6z3z; Wed, 10 Feb 2016 13:42:32 +0100 (CET) Received: from boulder.se.axis.com (boulder.se.axis.com [10.0.2.104]) by bastet.se.axis.com (Postfix) with ESMTP id 6986B18114; Wed, 10 Feb 2016 13:42:32 +0100 (CET) Received: from boulder.se.axis.com (localhost [127.0.0.1]) by postfix.imss71 (Postfix) with ESMTP id 5330513D1; Wed, 10 Feb 2016 13:42:32 +0100 (CET) Received: from seth.se.axis.com (seth.se.axis.com [10.0.2.172]) by boulder.se.axis.com (Postfix) with ESMTP id 47E9AD9; Wed, 10 Feb 2016 13:42:32 +0100 (CET) Received: from lnxlarper1.se.axis.com (lnxlarper1.se.axis.com [10.88.41.2]) by seth.se.axis.com (Postfix) with ESMTP id 41DB23E4EC; Wed, 10 Feb 2016 13:42:32 +0100 (CET) Received: by lnxlarper1.se.axis.com (Postfix, from userid 20456) id 3CDB0800FB; Wed, 10 Feb 2016 13:42:32 +0100 (CET) From: Lars Persson To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/8] clk: add artpec-6 pll1 clock driver Date: Wed, 10 Feb 2016 13:41:51 +0100 Message-Id: <30bfa3b9a237699a7a2078c51903238aa330b992.1455107681.git.larper@axis.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160210_044254_551176_4F67B565 X-CRM114-Status: GOOD ( 15.17 ) X-Spam-Score: -2.2 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, Lars Persson , linux-kernel@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PLL1 clock is a fixed-factor clock with factors derived from boot mode pins. This driver is a simple wrapper to register the fixed factor clock according to the pin settings. Signed-off-by: Lars Persson --- drivers/clk/Makefile | 1 + drivers/clk/clk-artpec6.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 drivers/clk/clk-artpec6.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index b038e36..388f0cf 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ endif # hardware specific clock types # please keep this section sorted lexicographically by file/directory path name +obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o diff --git a/drivers/clk/clk-artpec6.c b/drivers/clk/clk-artpec6.c new file mode 100644 index 0000000..3664c44 --- /dev/null +++ b/drivers/clk/clk-artpec6.c @@ -0,0 +1,70 @@ +/* + * ARTPEC-6 clock initialization + * + * Copyright 2015 Axis Comunications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +static void __init of_artpec6_pll1_setup(struct device_node *np) +{ + void __iomem *devstat; + struct clk *clk; + const char *clk_name = np->name; + const char *parent_name; + u32 pll_mode, pll_m, pll_n; + + parent_name = of_clk_get_parent_name(np, 0); + + devstat = of_iomap(np, 0); + if (devstat == NULL) { + pr_err("error to ioremap DEVSTAT\n"); + return; + } + + /* DEVSTAT register contains PLL settings */ + pll_mode = (readl(devstat) >> 6) & 3; + iounmap(devstat); + + /* + * pll1 settings are designed for different DDR speeds using a fixed + * 50MHz external clock. However, a different external clock could be + * used on different boards. + * CPU clock is half the DDR clock. + */ + switch (pll_mode) { + case 0: /* DDR3-2133 mode */ + pll_m = 4; + pll_n = 85; + break; + case 1: /* DDR3-1866 mode */ + pll_m = 6; + pll_n = 112; + break; + case 2: /* DDR3-1600 mode */ + pll_m = 4; + pll_n = 64; + break; + case 3: /* DDR3-1333 mode */ + pll_m = 8; + pll_n = 106; + break; + } + /* ext_clk is defined in device tree */ + clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, + pll_n, pll_m); + if (IS_ERR(clk)) { + pr_err("%s not registered\n", clk_name); + return; + } + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(artpec6_pll1, "axis,artpec6-pll1-clock", of_artpec6_pll1_setup);