From patchwork Wed May 7 21:15:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 4132071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 96E42BFF02 for ; Wed, 7 May 2014 21:17:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 98B562024D for ; Wed, 7 May 2014 21:17:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2FF520222 for ; Wed, 7 May 2014 21:17:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wi9BP-0001e0-Cc; Wed, 07 May 2014 21:15:19 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wi9BL-0000HK-E2 for linux-arm-kernel@lists.infradead.org; Wed, 07 May 2014 21:15:16 +0000 Received: from 146-52-69-41-dynip.superkabel.de ([146.52.69.41] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1Wi9Ay-00038g-Ie; Wed, 07 May 2014 23:14:52 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Mike Turquette Subject: [PATCH v2 09/11] ARM: dts: rk3188: add cru node and update device clocks to use it Date: Wed, 07 May 2014 23:15:30 +0200 Message-ID: <3177977.6ZVr2dKNOF@diego> User-Agent: KMail/4.11.5 (Linux/3.13-1-amd64; KDE/4.11.3; x86_64; ; ) In-Reply-To: <3477211.Gkyeur83TV@diego> References: <3477211.Gkyeur83TV@diego> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140507_141515_657198_E71305FD X-CRM114-Status: UNSURE ( 9.02 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) Cc: arm@kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a node for the clock and reset unit on rk3188 SoCs and updates the device nodes retrieve their clocks from there, instead of the previous gate clock nodes. As the clocks diverge a bit until rk3066 can catch up, the shared nodes between rk3066 and rk3188 get separated clocks-properties in the rk3188.dtsi. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 55 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index bb36596..dc3e986 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "rk3xxx.dtsi" #include "rk3188-clocks.dtsi" @@ -54,10 +55,12 @@ soc { global-timer@1013c200 { interrupts = ; + clocks = <&cru CORE_PERI>; }; local-timer@1013c600 { interrupts = ; + clocks = <&cru CORE_PERI>; }; sram: sram@10080000 { @@ -73,6 +76,50 @@ }; }; + uart0: serial@10124000 { + clocks = <&cru SCLK_UART0>; + }; + + uart1: serial@10126000 { + clocks = <&cru SCLK_UART1>; + }; + + uart2: serial@20064000 { + clocks = <&cru SCLK_UART2>; + }; + + uart3: serial@20068000 { + clocks = <&cru SCLK_UART3>; + }; + + dwmmc@10214000 { + clocks = <&cru HCLK_MMC0>, <&cru SCLK_MMC0>; + clock-names = "biu", "ciu"; + }; + + dwmmc@10218000 { + clocks = <&cru HCLK_MMC1>, <&cru SCLK_MMC1>; + clock-names = "biu", "ciu"; + }; + + cru: cru@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>, + <0x200080ac 0x4>; + + #clock-cells = <1>; + #reset-cells = <1>; + + #rockchip,armclk-cells = <3>; + rockchip,armclk-divider-table = <1608000 2 3>, + <1416000 2 3>, + <1200000 2 3>, + <1008000 2 3>, + < 816000 2 3>, + < 504000 1 3>, + < 312000 0 1>; + }; + pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; reg = <0x20008000 0xa0>, @@ -87,7 +134,7 @@ reg = <0x2000a000 0x100>, <0x20004064 0x8>; interrupts = ; - clocks = <&clk_gates8 9>; + clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -100,7 +147,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = ; - clocks = <&clk_gates8 10>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -113,7 +160,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = ; - clocks = <&clk_gates8 11>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -126,7 +173,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; - clocks = <&clk_gates8 12>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>;