From patchwork Thu May 23 15:07:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SARTRE Leo X-Patchwork-Id: 2607641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id EBE6CDFB78 for ; Thu, 23 May 2013 15:16:23 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfXFb-00057u-IF; Thu, 23 May 2013 15:16:19 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfXFY-0008WO-RO; Thu, 23 May 2013 15:16:16 +0000 Received: from mail1.adetelgroup.com ([109.7.94.227]) by merlin.infradead.org with smtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UfXFV-0008VY-3y for linux-arm-kernel@lists.infradead.org; Thu, 23 May 2013 15:16:13 +0000 Received: from mail.adetelgroup.com ([192.168.102.3]) by mail1.adetelgroup.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 23 May 2013 17:10:22 +0200 X-MimeOLE: Produced By Microsoft Exchange V6.5 Received: from 192.168.113.1 ([192.168.113.1]) by frontmail.adetel.com ([192.168.102.3]) with Microsoft Exchange Server HTTP-DAV ; Thu, 23 May 2013 15:10:06 +0000 MIME-Version: 1.0 X-Mailer: git-send-email 1.7.10.4 Content-class: urn:content-classes:message Subject: [PATCH] Add congatec conga-QEVAL minimal board support Date: Thu, 23 May 2013 17:07:29 +0200 Message-ID: <3465D313FDFB824F9A9C8CD24FA4F6BC0108CD11@frontmail.adetel.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] Add congatec conga-QEVAL minimal board support Thread-Index: Ac5Xx536W9adQE5wQMu5gj2lnKnRvQ== From: "SARTRE Leo" To: X-OriginalArrivalTime: 23 May 2013 15:10:22.0416 (UTC) FILETIME=[A553BD00:01CE57C7] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130523_111613_261293_C38A24DD X-CRM114-Status: GOOD ( 10.91 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- 2.0 FSL_HELO_BARE_IP_2 FSL_HELO_BARE_IP_2 -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux@arm.linux.org.uk, SARTRE Leo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Conga-QEVAL is a Qseven Evaluation Carrier board, manufactured by Congatec, it can be used with conga-QMX6 modules based on Freescale's i.MX6 ARM processors. More details can be found on the manufacturer's web site: for the board: http://www.congatec.com/en/products/accessories/dView/conga-qeval.html for the module: http://www.congatec.com/en/products/qseven/dView/conga-qmx6.html imx6q-congatec.dts: Add minimal congatec device tree (usb, fec, spi andusdhc) mach-imx6q.c : Add fixup function for micrel KSZ9031RNX Signed-off-by: Leo Sartre --- arch/arm/boot/dts/imx6q-congatec.dts | 92 ++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mach-imx6q.c | 41 +++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-congatec.dts diff --git a/arch/arm/boot/dts/imx6q-congatec.dts b/arch/arm/boot/dts/imx6q-congatec.dts new file mode 100644 index 0000000..d54d31a --- /dev/null +++ b/arch/arm/boot/dts/imx6q-congatec.dts @@ -0,0 +1,92 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * Copyright 2013 Adeneo Embedded + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" + +/ { + model = "Congatec i.MX6 Quad QSEVEN eval Board"; + compatible = "cgt,imx6q-qmx6", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + }; + +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf032b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000 + MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000 + MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + }; +}; + + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + cd-gpios = <&gpio2 6 0>; + wp-gpios = <&gpio2 7 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; +}; diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 5536fd8..7de4208 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -96,6 +96,36 @@ soft: soft_restart(0); } +/* For congatec qmx6 board, fixup micrel KSZ9031RNX */ +static int ksz9031rnx_phy_fixup(struct phy_device *phydev) +{ + if (IS_BUILTIN(CONFIG_PHYLIB)) { + /* adjust KSZ9031 ethernet phy */ + phy_write(phydev, 0x0d, 0x2); + phy_write(phydev, 0x0e, 0x4); + phy_write(phydev, 0x0d, 0xc002); + phy_write(phydev, 0x0e, 0x0000); + + phy_write(phydev, 0x0d, 0x2); + phy_write(phydev, 0x0e, 0x5); + phy_write(phydev, 0x0d, 0xc002); + phy_write(phydev, 0x0e, 0x0000); + + phy_write(phydev, 0x0d, 0x2); + phy_write(phydev, 0x0e, 0x6); + phy_write(phydev, 0x0d, 0xc002); + phy_write(phydev, 0x0e, 0xffff); + + phy_write(phydev, 0x0d, 0x2); + phy_write(phydev, 0x0e, 0x8); + phy_write(phydev, 0x0d, 0xc002); + phy_write(phydev, 0x0e, 0x3fff); + phy_write(phydev, 0x0d, 0x0); + } + + return 0; +} + /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { @@ -145,6 +175,14 @@ static void __init imx6q_sabrelite_init(void) imx6q_sabrelite_cko1_setup(); } +static void __init imx6q_cgtqmx6_init(void) +{ + if (IS_BUILTIN(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, + ksz9031rnx_phy_fixup); + imx6q_sabrelite_cko1_setup(); +} + static void __init imx6q_1588_init(void) { struct regmap *gpr; @@ -166,6 +204,9 @@ static void __init imx6q_init_machine(void) if (of_machine_is_compatible("fsl,imx6q-sabrelite")) imx6q_sabrelite_init(); + if (of_machine_is_compatible("cgt,imx6q-qmx6")) + imx6q_cgtqmx6_init(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); imx_anatop_init();