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Thu, 9 Mar 2023 02:54:34 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 02/14] iommufd: Add nesting related data structures for ARM SMMUv3 Date: Thu, 9 Mar 2023 02:53:38 -0800 Message-ID: <364cfbe5b228ab178093db2de13fa3accf7a6120.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|DM6PR12MB4433:EE_ X-MS-Office365-Filtering-Correlation-Id: 2cae24fa-5983-45f2-41fe-08db208cb0e7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fbuc96ajFZNCTLGRhJYRiDZtERvpg+2CpgHugDlVXgjtY7drdOzmNs5FpXNYS8JA0bma08RawTqB4/1+CtYZCdw13m6KsIKaH7/yzX0UsErKAya+j+1Pga0ncqaJml3QeDFFz7JeqSv9Lc2+kiQAK3tzFqhRTZlsjUrNqqVDHKzMGUmf3NRSo2StJtEwBgjvWCECoHLnG2fKJ8qQkLlCwlvwP9f86DcpCYrScFMiZMEUqR/NY88by5b9e2hYTAagN2yEmJHWAeqHttmTVG6Fbhhg3+a6Q71C97crK8VTjik1e9/1DhAuiyMT1e/D8bpALzpmj7SLAN+Sfq1VNYy0hCd3t+KuN+2Gk6XaSQfUzBA+uLll1IgPamTs9hyXPs55g9ux924KpMV4ojlomOM5siZB+XLVpLbYJK56+UFLON5bNOHoT+gbiD7lG+U9yue8U7+Taer1qW72MGNMBWAv/0HAjeyV0q4IgcDwMccH33nfqAXmLvUxqrgGZfERNtCeOsl2ZBpD9tKfUhdMuzJBWrUgjL4iYll2IAu0LXXLB4O4Tnm+DXnDFlkxAWRIpVBNM5nr+bDYH3GcBKiIO5M9QIPkShwFmUQK3pTIKJL0Ez2tPS/iWu5Rw4edHUkk3Gy6jp5yku/I89E+/2cu607gbi9RUp9xvrWm5pvcbHc8QIuQIb0jgAd6YUmZ0ZKyxkQNJzhK2f/OI6adQx9HTSUZQX5UmaFkN5Lm8D0VriHxpZsEt7Rdhhh/EErd3kQxBOUjLE37EpQmflp1MAnud82K9C9IjL4psO0iCqj7OXR0BTf8V9XJyVr9dPkItxeItS8R X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(136003)(396003)(376002)(39860400002)(451199018)(46966006)(36840700001)(40470700004)(8936002)(36756003)(7416002)(5660300002)(26005)(36860700001)(82740400003)(7636003)(82310400005)(336012)(426003)(47076005)(83380400001)(186003)(2616005)(40480700001)(54906003)(86362001)(316002)(110136005)(41300700001)(8676002)(70206006)(70586007)(4326008)(40460700003)(356005)(7696005)(478600001)(2906002)(473944003)(414714003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:43.6481 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2cae24fa-5983-45f2-41fe-08db208cb0e7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4433 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230309_025449_877370_0EC51687 X-CRM114-Status: GOOD ( 13.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the following data structures for corresponding ioctls: iommu_hwpt_arm_smmuv3 => IOMMUFD_CMD_HWPT_ALLOC iommu_hwpt_invalidate_arm_smmuv3 => IOMMUFD_CMD_HWPT_INVALIDATE Also, add IOMMU_HW_INFO_TYPE_ARM_SMMUV3 and IOMMU_PGTBL_TYPE_ARM_SMMUV3_S1 to the header and corresponding type/size arrays. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/hw_pagetable.c | 4 +++ drivers/iommu/iommufd/main.c | 1 + include/uapi/linux/iommufd.h | 50 ++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c index 8f9985bddeeb..5e798b2f9a3a 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -173,6 +173,7 @@ iommufd_hw_pagetable_alloc(struct iommufd_ctx *ictx, struct iommufd_ioas *ioas, static const size_t iommufd_hwpt_alloc_data_size[] = { [IOMMU_HWPT_TYPE_DEFAULT] = 0, [IOMMU_HWPT_TYPE_VTD_S1] = sizeof(struct iommu_hwpt_intel_vtd), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] = sizeof(struct iommu_hwpt_arm_smmuv3), }; /* @@ -183,6 +184,8 @@ const u64 iommufd_hwpt_type_bitmaps[] = { [IOMMU_HW_INFO_TYPE_DEFAULT] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT), [IOMMU_HW_INFO_TYPE_INTEL_VTD] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | BIT_ULL(IOMMU_HWPT_TYPE_VTD_S1), + [IOMMU_HW_INFO_TYPE_ARM_SMMUV3] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | + BIT_ULL(IOMMU_HWPT_TYPE_ARM_SMMUV3), }; /* Return true if type is supported, otherwise false */ @@ -329,6 +332,7 @@ int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd) */ static const size_t iommufd_hwpt_invalidate_info_size[] = { [IOMMU_HWPT_TYPE_VTD_S1] = sizeof(struct iommu_hwpt_invalidate_intel_vtd), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] = sizeof(struct iommu_hwpt_invalidate_arm_smmuv3), }; int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 514db4c26927..0b0097af7c86 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -280,6 +280,7 @@ union ucmd_buffer { * path. */ struct iommu_hwpt_invalidate_intel_vtd vtd; + struct iommu_hwpt_invalidate_arm_smmuv3 smmuv3; }; struct iommufd_ioctl_op { diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 2a6c326391b2..0d5551b1b2be 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -352,10 +352,13 @@ struct iommu_vfio_ioas { * enum iommu_hwpt_type - IOMMU HWPT Type * @IOMMU_HWPT_TYPE_DEFAULT: default * @IOMMU_HWPT_TYPE_VTD_S1: Intel VT-d stage-1 page table + * @IOMMU_HWPT_TYPE_ARM_SMMUV3: ARM SMMUv3 stage-1 Context Descriptor + * table */ enum iommu_hwpt_type { IOMMU_HWPT_TYPE_DEFAULT, IOMMU_HWPT_TYPE_VTD_S1, + IOMMU_HWPT_TYPE_ARM_SMMUV3, }; /** @@ -411,6 +414,28 @@ struct iommu_hwpt_intel_vtd { __u32 __reserved; }; +/** + * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 specific page table data + * + * @flags: page table entry attributes + * @s2vmid: Virtual machine identifier + * @s1ctxptr: Stage-1 context descriptor pointer + * @s1cdmax: Number of CDs pointed to by s1ContextPtr + * @s1fmt: Stage-1 Format + * @s1dss: Default substream + */ +struct iommu_hwpt_arm_smmuv3 { +#define IOMMU_SMMUV3_FLAG_S2 (1 << 0) /* if unset, stage-1 */ +#define IOMMU_SMMUV3_FLAG_VMID (1 << 1) /* vmid override */ + __u64 flags; + __u32 s2vmid; + __u32 __reserved; + __u64 s1ctxptr; + __u64 s1cdmax; + __u64 s1fmt; + __u64 s1dss; +}; + /** * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC) * @size: sizeof(struct iommu_hwpt_alloc) @@ -446,6 +471,8 @@ struct iommu_hwpt_intel_vtd { * +------------------------------+-------------------------------------+-----------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_intel_vtd | HWPT | * +------------------------------+-------------------------------------+-----------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_arm_smmuv3 | IOAS/HWPT | + * +------------------------------+-------------------------------------------------+ */ struct iommu_hwpt_alloc { __u32 size; @@ -463,10 +490,12 @@ struct iommu_hwpt_alloc { /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type + * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_DEFAULT, IOMMU_HW_INFO_TYPE_INTEL_VTD, + IOMMU_HW_INFO_TYPE_ARM_SMMUV3, }; /** @@ -591,6 +620,25 @@ struct iommu_hwpt_invalidate_intel_vtd { __u64 nb_granules; }; +/** + * struct iommu_hwpt_invalidate_arm_smmuv3 - ARM SMMUv3 cahce invalidation info + * @flags: boolean attributes of cache invalidation command + * @opcode: opcode of cache invalidation command + * @ssid: SubStream ID + * @granule_size: page/block size of the mapping in bytes + * @range: IOVA range to invalidate + */ +struct iommu_hwpt_invalidate_arm_smmuv3 { +#define IOMMU_SMMUV3_CMDQ_TLBI_VA_LEAF (1 << 0) + __u64 flags; + __u8 opcode; + __u8 padding[3]; + __u32 asid; + __u32 ssid; + __u32 granule_size; + struct iommu_iova_range range; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) @@ -609,6 +657,8 @@ struct iommu_hwpt_invalidate_intel_vtd { * +------------------------------+----------------------------------------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_invalidate_intel_vtd | * +------------------------------+----------------------------------------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_invalidate_arm_smmuv3| + * +------------------------------+----------------------------------------+ */ struct iommu_hwpt_invalidate { __u32 size;