| Message ID | 398ca9f17bda638e05e97f258fb4e6d27ac828db.1437059658.git.cyrille.pitchen@atmel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote: Hi! > Both the SPI controller and the NOR flash memory need to agree on the > number of dummy cycles to use for Fast Read commands. For Spansion > memories, this number of dummy cycles is not given directly but through a > so called "latency code". > The latency code can be found into the memory datasheet and depends on the > SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate > mode. Shouldn't you be able to derive the latency code from the above information, which you already know then ? Best regards, Marek Vasut
Hi Marek, Le 16/07/2015 19:44, Marek Vasut a écrit : > On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote: > > Hi! > >> Both the SPI controller and the NOR flash memory need to agree on the >> number of dummy cycles to use for Fast Read commands. For Spansion >> memories, this number of dummy cycles is not given directly but through a >> so called "latency code". >> The latency code can be found into the memory datasheet and depends on the >> SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate >> mode. > > Shouldn't you be able to derive the latency code from the above information, > which you already know then ? Yes I agree with you; this could have been done adding static tables inside the driver instead of creating a new DT property dedicated to Spansion memories. When I wrote this patch, I had a close look at the s25fl512s datasheet but only overviewed few datasheets for other Spansion QSPI flash memories. So I don't know whether a single latency code table could be shared among all Spansion memories or many tables should be added to support different memory models. That's why I've chosen to add a dedicated DT property to support Spansion memories as it avoids to add tables to guess the proper latency code to be used. I thought it would be more flexible. Maybe I will remove the support of Spansion QSPI memories from this series for now. Their support can still be implemented later. Anyway, thanks for your review :) > > Best regards, > Marek Vasut > Best Regards, Cyrille
On Monday, July 20, 2015 at 11:23:39 AM, Cyrille Pitchen wrote: > Hi Marek, Hi! > Le 16/07/2015 19:44, Marek Vasut a écrit : > > On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote: > > > > Hi! > > > >> Both the SPI controller and the NOR flash memory need to agree on the > >> number of dummy cycles to use for Fast Read commands. For Spansion > >> memories, this number of dummy cycles is not given directly but through > >> a so called "latency code". > >> The latency code can be found into the memory datasheet and depends on > >> the SPI clock frequency, the Fast Read op code and the Single/Dual Data > >> Rate mode. > > > > Shouldn't you be able to derive the latency code from the above > > information, which you already know then ? > > Yes I agree with you; this could have been done adding static tables inside > the driver instead of creating a new DT property dedicated to Spansion > memories. OK, I see now. The latency code can not be calculed from "SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate mode" easily, you need to index into some table to obtain some ad-hoc value. Got it. Sorry for the noise! > When I wrote this patch, I had a close look at the s25fl512s datasheet but > only overviewed few datasheets for other Spansion QSPI flash memories. So > I don't know whether a single latency code table could be shared among all > Spansion memories or many tables should be added to support different > memory models. > > That's why I've chosen to add a dedicated DT property to support Spansion > memories as it avoids to add tables to guess the proper latency code to be > used. I thought it would be more flexible. > > Maybe I will remove the support of Spansion QSPI memories from this series > for now. Their support can still be implemented later. > > Anyway, thanks for your review :) Let's wait for more comments :) Best regards, Marek Vasut
diff --git a/Documentation/devicetree/bindings/mtd/spansion-nor.txt b/Documentation/devicetree/bindings/mtd/spansion-nor.txt new file mode 100644 index 000000000000..a55c62db0e6f --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/spansion-nor.txt @@ -0,0 +1,22 @@ +* Spansion NOR flash + +Optional properties: +- spansion,latency-code : Only used when the "m25p,num-dummy-cycles" property is + set. The Spansion latency code tells the NOR flash + memory the number of dummy cycles to expect for each + Fast Read command. The value to be used is provided by + tables in the memory datasheet and depends on the SPI + clock frequency and on the Single/Dual Data Rate mode. + Then the value of "m25p,num-dummy-cycles" property + should match the (Fast) Read command to be used for + the chosen latency code. + +Example: + + m25p80@0 { + compatible = "spansion,s25fl512s"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,num-dummy-cycles = <8>; + spansion,latency-code = <2>; + };
Both the SPI controller and the NOR flash memory need to agree on the number of dummy cycles to use for Fast Read commands. For Spansion memories, this number of dummy cycles is not given directly but through a so called "latency code". The latency code can be found into the memory datasheet and depends on the SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate mode. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> --- .../devicetree/bindings/mtd/spansion-nor.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/spansion-nor.txt