From patchwork Wed Dec 6 00:57:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 13480925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C78EC10DC3 for ; Wed, 6 Dec 2023 00:58:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dFOcnho/etkrjTJHpi+7iPMgfLRS0Z+hZN/kCT3J2ys=; b=CrLLvlBVLmYWCX DuMU2bQLKQmReeI13RpX1H+nUigiFThepNmy3Z/91zPjeBrFXxW/t6IHQa9vSc+ZTd1Glmjva1H2N YQGWpiDGr72sz3EhA0dvCXNg401DAW8EGL+VBDtInRfasJ/UbRFJ+cXCBgbDfxuhYc5Pbk3gZjVj4 wtU6MZ6fp0OpZ/MPkO0jYOKM20jDX3mh0NScW/FTXLrwlvyGkBumhKt4gzqGhCtc2yC1/RICCNQv9 NGEA7iOHoUJVlREWEMW3ikD6VvzFNQT9ZIs7J7fwO2Hsi/24R9n6Yfmk8ceKH/P8UTXXi1dwk2PEx Go94eP6U6+TIiy1y2Tzw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rAgEN-008kUD-35; Wed, 06 Dec 2023 00:57:39 +0000 Received: from pidgin.makrotopia.org ([185.142.180.65]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rAgEK-008kSd-2C; Wed, 06 Dec 2023 00:57:38 +0000 Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1rAgE7-0002TW-12; Wed, 06 Dec 2023 00:57:24 +0000 Date: Wed, 6 Dec 2023 00:57:20 +0000 From: Daniel Golle To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Sabrina Dubroca , Daniel Golle , Jianhui Zhao , Chen-Yu Tsai , "Garmin.Chang" , Sam Shih , Frank Wunderlich , Dan Carpenter , James Liao , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org Subject: [PATCH v3 3/4] clk: mediatek: Add pcw_chg_shift control Message-ID: <40981d0bb722eb509628bcf82c31f632e4cf747a.1701823757.git.daniel@makrotopia.org> References: <23bc89d407e7797e97b703fa939b43bfe79296ce.1701823757.git.daniel@makrotopia.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <23bc89d407e7797e97b703fa939b43bfe79296ce.1701823757.git.daniel@makrotopia.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231205_165736_718431_F5D5D0CF X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Sam Shih Introduce pcw_chg_shfit control to optionally use that instead of the hardcoded PCW_CHG_MASK macro. This will needed for clocks on the MT7988 SoC. Signed-off-by: Sam Shih Signed-off-by: Daniel Golle --- v3: use git --from ... v2: no changes drivers/clk/mediatek/clk-pll.c | 5 ++++- drivers/clk/mediatek/clk-pll.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 513ab6b1b3229..9f08bc5d2a8a2 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -114,7 +114,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, pll->data->pcw_shift); val |= pcw << pll->data->pcw_shift; writel(val, pll->pcw_addr); - chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; + if (pll->data->pcw_chg_shift) + chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); + else + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; writel(chg, pll->pcw_chg_addr); if (pll->tuner_addr) writel(val + 1, pll->tuner_addr); diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f17278ff15d78..d28d317e84377 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -44,6 +44,7 @@ struct mtk_pll_data { u32 pcw_reg; int pcw_shift; u32 pcw_chg_reg; + int pcw_chg_shift; const struct mtk_pll_div_table *div_table; const char *parent_name; u32 en_reg;