| Message ID | 4355781.cnmcVo5AVu@diego (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Heiko, On Tue, Jul 15, 2014 at 4:01 PM, Heiko Stübner <heiko@sntech.de> wrote: > Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > arch/arm/mach-rockchip/Kconfig | 1 + > arch/arm/mach-rockchip/rockchip.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig > index e4564c2..d168669 100644 > --- a/arch/arm/mach-rockchip/Kconfig > +++ b/arch/arm/mach-rockchip/Kconfig > @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP > select ARCH_REQUIRE_GPIOLIB > select ARM_GIC > select CACHE_L2X0 > + select HAVE_ARM_ARCH_TIMER Do we want to think about allowing someone to enable the A9-based Rockchip SoCs separately than the A12-based ones? I know it doesn't hurt to have the arch timer code present on A9 SoCs (it will figure things out at runtime), but people trying to build an A9-based system might not want the extra code? Anyway, I don't feel strongly about it, so: Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org>
Am Mittwoch, 16. Juli 2014, 12:57:21 schrieb Doug Anderson: > Heiko, > > On Tue, Jul 15, 2014 at 4:01 PM, Heiko Stübner <heiko@sntech.de> wrote: > > Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible. > > > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > --- > > > > arch/arm/mach-rockchip/Kconfig | 1 + > > arch/arm/mach-rockchip/rockchip.c | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/arch/arm/mach-rockchip/Kconfig > > b/arch/arm/mach-rockchip/Kconfig index e4564c2..d168669 100644 > > --- a/arch/arm/mach-rockchip/Kconfig > > +++ b/arch/arm/mach-rockchip/Kconfig > > @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP > > > > select ARCH_REQUIRE_GPIOLIB > > select ARM_GIC > > select CACHE_L2X0 > > > > + select HAVE_ARM_ARCH_TIMER > > Do we want to think about allowing someone to enable the A9-based > Rockchip SoCs separately than the A12-based ones? I know it doesn't > hurt to have the arch timer code present on A9 SoCs (it will figure > things out at runtime), but people trying to build an A9-based system > might not want the extra code? > > Anyway, I don't feel strongly about it, so: I've also thought about this previously. Personally I would want to wait with introducing more complexity here until someone comes along with a use case. Simply because we're talking about 7kb (stripped) for the arch-timer and machines with >1GB of memory. So I'm not adverse to it, but I guess it will make more sense when more soc- specific code lands - suspend stuff for example. But I think we should be able to drop the dw_apb_timer altogether, as it stems from a time before I found the global-timer informations and all A9 SoCs should be able to use this one instead. > > Reviewed-by: Doug Anderson <dianders@chromium.org> > Tested-by: Doug Anderson <dianders@chromium.org>
On Wed, Jul 16, 2014 at 08:57:21PM +0100, Doug Anderson wrote: > Heiko, > > On Tue, Jul 15, 2014 at 4:01 PM, Heiko Stübner <heiko@sntech.de> wrote: > > Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible. > > > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > --- > > arch/arm/mach-rockchip/Kconfig | 1 + > > arch/arm/mach-rockchip/rockchip.c | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig > > index e4564c2..d168669 100644 > > --- a/arch/arm/mach-rockchip/Kconfig > > +++ b/arch/arm/mach-rockchip/Kconfig > > @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP > > select ARCH_REQUIRE_GPIOLIB > > select ARM_GIC > > select CACHE_L2X0 > > + select HAVE_ARM_ARCH_TIMER > > Do we want to think about allowing someone to enable the A9-based > Rockchip SoCs separately than the A12-based ones? I know it doesn't > hurt to have the arch timer code present on A9 SoCs (it will figure > things out at runtime), but people trying to build an A9-based system > might not want the extra code? More likely, people using the A12-based system won't want the CACHE_L2X0 code (which adds an outer_cache.sync check to wmb()). Will
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index e4564c2..d168669 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -6,6 +6,7 @@ config ARCH_ROCKCHIP select ARCH_REQUIRE_GPIOLIB select ARM_GIC select CACHE_L2X0 + select HAVE_ARM_ARCH_TIMER select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select DW_APB_TIMER_OF diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 968cc34..8ab9e0e 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -29,6 +29,7 @@ static const char * const rockchip_board_dt_compat[] = { "rockchip,rk3066a", "rockchip,rk3066b", "rockchip,rk3188", + "rockchip,rk3288", NULL, };
Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rockchip.c | 1 + 2 files changed, 2 insertions(+)