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Tue, 1 May 2018 05:29:47 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 1 May 2018 05:29:47 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w41ATep1029225; Tue, 1 May 2018 05:29:43 -0500 Subject: Re: [PATCH 01/12] mtd: nand: davinci: store the core chipselect number in platform data From: Sekhar Nori To: Bartosz Golaszewski , Kevin Hilman , Russell King , Boris Brezillon , Richard Weinberger , David Woodhouse , Brian Norris , Marek Vasut , Tony Lindgren , Krzysztof Kozlowski References: <20180430082453.8091-1-brgl@bgdev.pl> <20180430082453.8091-2-brgl@bgdev.pl> <3dccc5af-2df1-8374-e4e8-0a8b9ea1ae99@ti.com> <8b7e4588-5a35-6c18-fe60-148d6ccf778c@ti.com> Message-ID: <447b4f2f-27c8-f552-d058-3b2eba71a765@ti.com> Date: Tue, 1 May 2018 15:59:40 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <8b7e4588-5a35-6c18-fe60-148d6ccf778c@ti.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180501_033026_485839_FB17721A X-CRM114-Status: GOOD ( 26.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Tuesday 01 May 2018 03:23 PM, Sekhar Nori wrote: > On Tuesday 01 May 2018 02:55 PM, Sekhar Nori wrote: >> On Monday 30 April 2018 01:54 PM, Bartosz Golaszewski wrote: >>> From: Bartosz Golaszewski >>> >>> We have the 'ti,davinci-chipselect' property in the device tree, but >>> when using platform data the driver silently uses the id field of >>> struct platform_device as the chipselect. This is confusing and we >>> almost broke the nand support again recently after converting the >>> platform to common clock framework (which changed the device id in the >>> clock lookup - the problem is gone now that we no longer acquire the >>> clock in the nand driver. >>> >>> This patch adds a new filed - core_chipsel - to the platform_data. >> >> s/filed/field >> >>> Subsequent patches will convert the platforms to using this new field. >> >> Can you add a comment for this new field too, like how we have for most >> other fields? >> >> Curious on what 'core' in core_chipsel means. Something to do with >> chip-select offset we have on DA850? > > Looks like you may have just picked the terminology from DaVinci NAND > driver (introduced back in 2009). But in this context, it means the > 0-indexed chip-select number that of the asynchronous memory interface > to which the NAND device is connected. > > So, may be a comment here will suffice. This is what I committed: --8<-- commit 533d93703fa717fdf74c4fb711c868c4fdc8b475 (HEAD -> refs/heads/v4.18/nand-cs-simplification) Author: Bartosz Golaszewski AuthorDate: Mon Apr 30 10:24:42 2018 +0200 Commit: Sekhar Nori CommitDate: Tue May 1 15:57:47 2018 +0530 mtd: nand: davinci: store the core chipselect number in platform data We have the 'ti,davinci-chipselect' property in the device tree, but when using platform data the driver silently uses the id field of struct platform_device as the chipselect. This is confusing and we almost broke the nand support again recently after converting the platform to common clock framework (which changed the device id in the clock lookup - the problem is gone now that we no longer acquire the clock in the nand driver. This patch adds a new field - core_chipsel - to the platform_data. Subsequent patches will convert the platforms to using this new field. Signed-off-by: Bartosz Golaszewski Signed-off-by: Sekhar Nori diff --git a/include/linux/platform_data/mtd-davinci.h b/include/linux/platform_data/mtd-davinci.h index f1a2cf655bdb..1bbfa27cccb4 100644 --- a/include/linux/platform_data/mtd-davinci.h +++ b/include/linux/platform_data/mtd-davinci.h @@ -56,6 +56,16 @@ struct davinci_nand_pdata { /* platform_data */ uint32_t mask_ale; uint32_t mask_cle; + /* + * 0-indexed chip-select number of the asynchronous + * interface to which the NAND device has been connected. + * + * So, if you have NAND connected to CS3 of DA850, you + * will pass '1' here. Since the asynchronous interface + * on DA850 starts from CS2. + */ + uint32_t core_chipsel; + /* for packages using two chipselects */ uint32_t mask_chipsel;