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Thu, 15 Aug 2024 17:55:40 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v12 03/10] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_build_sync_cmd Date: Thu, 15 Aug 2024 17:55:24 -0700 Message-ID: <48cc52863e8a076c62a5c6bc6c7ccc7836de1648.1723754745.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E66:EE_|SJ1PR12MB6097:EE_ X-MS-Office365-Filtering-Correlation-Id: dab52d22-5b49-49fb-0201-08dcbd8e3039 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: Mhh+w+K1W4GwObnt1ARTbPcKsi7P1mhDZG/IANbfaINIzd+Et+E3DNi5FrmTioieT/cw8u6Mimlcs0tLzWw7ECvV840P7jHsonXRDwi1meBWPH8uybetc0Nt4eTouNSf3wYN8qgnXoJ6NUNu0I4c/Zf2DWQ/ymw9Q6rAey/LrWgyclygkpAEhUayoJzVTaECfkyBzyY7F6S6eUhviJs2sKIO4w+mWgFlt5opqtpIMbxd5guTSLbDxDEnZVWD+AYgGpuT5NIXaY98LIR+A6R2X00ICsSEFMT8wMIMl0RG3S0KQexdUi6W0KjgsyppvXx1RKgtVZD6PfIGtQ0++3itO7zdomEuY4yNd2WC5FdnfirlXmOahT7sAp0+FSm4ro6Za48yM4feHfkjA3ZcHxxS8ZjU//Ap8xlZWY/p4fWhFgJoHoXd2BmZLeuwmkpgNZyv607rQNIuKdLHp1o3Ce7dOSMrAfQhgL14D0WNb7IUSEplWyYMsOmapuj4CZUPCvTkGV6Zm1EP6SK/FN8BgjWNqJ7A8YHYIhMZPbdlBul7P18AYH0qPAIzxPsZR7tBjH/HuWxgBDI7dnwZh14Sg0KJUvlP2K2c4ucacjIAQCyqBrKUjL3qScdvUGrVEOcf4znWTuL2egz4WdW1VWZsahn5zfb3tu6qyi4zEZunizonT7sKBnmBGU1yE4ErH20cYDd/GrnYsrXtiw8+BWOnJ6yGkl3ml6vmgWsa22hhyyxWDxhMWJT6rCrbwotix+kp9HfvNot6+bO/WEl7Bed7OrKPED99bLl6onXC4mmyxRwus66MhzIRWs+DhFfPZy6GjiRj9SlHYKmvnB9TWHjeaM2774EmWKpe270Ovw2JFyNAUx3A3YrK9afRQIgPNfEYQDd/+jGwfmgvyddP4MHQ6ksnExTcZw8iLjFerudJMzWOJ0CFab1Z5SOvIkZYAkmGkXGFWmu/RwYyQsz77BlcSorIy19lNagH1ech3f3RtHY48vi29L05toaViSxtL4g9iimyP4aihy/9XjHm0qH68nPylbkrBg5p8QFHgSm4uLN4VFVFbKpEtapqdymS8I4GzgOhkYRnoATb/+Cr7RMlOxsdJkPsTe0CvK7V64vM0EsCbKqJrlRuvi+DnazC1IEt8PlC7zj9qhHfs4/g1Y+p9nb4JiRq70X/6QbQnYPfMRuThUxg8LcIaYj7d3rtq158HnHQin6InFuRbA+ZNh+SILIuhU00vbIxYvKXCXSp+sSP4MP4YY5o36YSJoJkvG1Va5jZbo5hJYuDiOa5DJrAewm3PNRgkc5ZOVerFVMWoIggNTXPy3jAkcJrkYxWi+MNxcWPrlMle+6bXMhqyOmfeqauVph2ofJFhklSG4OiXN8cK6HaeL3cx3zsZH5AGj905xpFd3QBPqpzrOYwR/Jl3SaGvImMMc7fcpa77QcgTMYxacXOJwmUI4K/txtVEzc37GxC X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 00:55:56.9940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dab52d22-5b49-49fb-0201-08dcbd8e3039 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6097 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_175606_807728_772EB7D2 X-CRM114-Status: GOOD ( 12.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension on NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC, v.s. standard SMMU CMDQ. Pass in the cmdq pointer directly, so the function can identify a different cmdq implementation. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f481d7be3d4e..d11362e9fc8a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -342,8 +342,10 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) } static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, - struct arm_smmu_queue *q, u32 prod) + struct arm_smmu_cmdq *cmdq, u32 prod) { + struct arm_smmu_queue *q = &cmdq->q; + cmd[1] = 0; cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | @@ -364,7 +366,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, } static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) + struct arm_smmu_cmdq *cmdq) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -372,6 +374,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", [CMDQ_ERR_CERROR_ATC_INV_IDX] = "ATC invalidate timeout", }; + struct arm_smmu_queue *q = &cmdq->q; int i; u64 cmd[CMDQ_ENT_DWORDS]; @@ -410,14 +413,14 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, cmdq, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); + __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); } /* @@ -780,7 +783,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n); if (sync) { prod = queue_inc_prod_n(&llq, n); - arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); + arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod); queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); /*