From patchwork Mon Aug 15 07:49:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas KANDAGATLA X-Patchwork-Id: 1066882 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7F7qwbF011853 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 15 Aug 2011 07:53:25 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QsryX-00064x-RU; Mon, 15 Aug 2011 07:52:46 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QsryX-0005Nh-Bs; Mon, 15 Aug 2011 07:52:45 +0000 Received: from eu1sys200aog104.obsmtp.com ([207.126.144.117]) by canuck.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1QsryT-0005NO-HJ for linux-arm-kernel@lists.infradead.org; Mon, 15 Aug 2011 07:52:42 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob104.postini.com ([207.126.147.11]) with SMTP ID DSNKTkjQPt87fhOOfVX5qGU7+9++QZJdgcLE@postini.com; Mon, 15 Aug 2011 07:52:41 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D3793C6; Mon, 15 Aug 2011 07:52:21 +0000 (GMT) Received: from mail7.sgp.st.com (mail7.sgp.st.com [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3CCC8197D; Mon, 15 Aug 2011 07:52:21 +0000 (GMT) Received: from [10.65.51.191] (king.bri.st.com [10.65.51.191]) by mail7.sgp.st.com (MOS 4.1.8-GA) with ESMTP id AJR88419 (AUTH srinivak); Mon, 15 Aug 2011 09:52:20 +0200 Message-ID: <4E48CF80.6070105@st.com> Date: Mon, 15 Aug 2011 08:49:20 +0100 From: Srinivas KANDAGATLA Organization: STMicroelectronics User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 To: Will Deacon , Russell King - ARM Linux Subject: Re: [PATCH kernel-3.0] arm:cache-l2x0: Fix L2 Cache size calculation. References: <1313142327-18320-1-git-send-email-srinivas.kandagatla@st.com> <20110812102020.GD14904@e102144-lin.cambridge.arm.com> <20110813084129.GM4775@n2100.arm.linux.org.uk> <20110814204851.GA1948@e102144-lin.cambridge.arm.com> In-Reply-To: <20110814204851.GA1948@e102144-lin.cambridge.arm.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110815_035241_821084_ECE48074 X-CRM114-Status: GOOD ( 27.01 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.117 listed in list.dnswl.org] Cc: "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: srinivas.kandagatla@st.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 15 Aug 2011 07:53:25 +0000 (UTC) Resending the patch with Acked by and CC lines in patch... Thanks, --srini Will Deacon wrote: > Hi Russell, > > On Sat, Aug 13, 2011 at 09:41:29AM +0100, Russell King - ARM Linux wrote: > >> On Fri, Aug 12, 2011 at 11:20:20AM +0100, Will Deacon wrote: >> >>> On Fri, Aug 12, 2011 at 10:45:27AM +0100, Srinivas KANDAGATLA wrote: >>> >>>> From: Srinivas Kandagatla >>>> >>>> This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and >>>> PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 >>>> bits. >>>> > > [...] > > >>> Please can you CC stable on this too? >>> >> It's probably better to ask people to add a Cc: line to the _attributations_ >> rather than telling them to CC the stable tree with their email, and then >> get a whinge from the stable maintainers about how that's not how to submit >> patches for stable trees. >> > > Of course, that's what I intended but unfortunately my choice of words > was ambiguous. > > Srinivas: can you add the CC stable line to your patch please and put it > into Russell's patch system? > > Thanks, > > Will > From 190ce84ccd8d73b997f00b51121a8583ff0f2a7f Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 12 Aug 2011 10:21:58 +0100 Subject: [PATCH kernel-3.0] arm:cache-l2x0: Fix L2 Cache size calculation. This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits. The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations. It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small) and also prints incorrect cachesize. Signed-off-by: Srinivas Kandagatla Acked-by: Will Deacon Cc: stable@kernel.org --- adding stable in CC.. Hi All, I found an bug in L2 Cache size calculation in cache-l2x0 code. According to ARM TRM for L2C-210, L2C-310 and PL310, the Auxiliary Control Register has 3bits [19:17] allocated for Way size,however the existing code only uses 2 bits to get this value from Aux control register. This results in incorrect cache size calculations. It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small). thanks, srini arch/arm/include/asm/hardware/cache-l2x0.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 16bd480..bfa706f 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -64,7 +64,7 @@ #define L2X0_AUX_CTRL_MASK 0xc0000fff #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 -#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) +#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 -- 1.6.3.3