From patchwork Sun Sep 4 10:13:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1123562 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p84AEJBq007503 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sun, 4 Sep 2011 10:14:39 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R09iG-00077L-3n; Sun, 04 Sep 2011 10:14:04 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R09iF-0007Sk-Oh; Sun, 04 Sep 2011 10:14:03 +0000 Received: from na3sys009aog123.obsmtp.com ([74.125.149.149]) by canuck.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1R09i9-0007SR-GN for linux-arm-kernel@lists.infradead.org; Sun, 04 Sep 2011 10:14:01 +0000 Received: from mail-gw0-f52.google.com ([74.125.83.52]) (using TLSv1) by na3sys009aob123.postini.com ([74.125.148.12]) with SMTP ID DSNKTmNPYsDO0URvguIq4jV4UcdRmZHdkqxp@postini.com; Sun, 04 Sep 2011 03:13:57 PDT Received: by gwj15 with SMTP id 15so4072547gwj.25 for ; Sun, 04 Sep 2011 03:13:54 -0700 (PDT) Received: by 10.151.13.8 with SMTP id q8mr514293ybi.445.1315131233933; Sun, 04 Sep 2011 03:13:53 -0700 (PDT) Received: from [172.24.137.49] (dragon.ti.com [192.94.94.33]) by mx.google.com with ESMTPS id 20sm5570366ant.22.2011.09.04.03.13.47 (version=SSLv3 cipher=OTHER); Sun, 04 Sep 2011 03:13:51 -0700 (PDT) Message-ID: <4E634F59.1010207@ti.com> Date: Sun, 04 Sep 2011 15:43:45 +0530 From: Santosh User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.18) Gecko/20110617 Thunderbird/3.1.11 MIME-Version: 1.0 To: Linus Walleij Subject: Re: [PATCH] ARM: l2x0: make sure I&D are not locked down on init References: <1315126872-3290-1-git-send-email-linus.walleij@stericsson.com> In-Reply-To: <1315126872-3290-1-git-send-email-linus.walleij@stericsson.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110904_061357_772820_0B74C790 X-CRM114-Status: GOOD ( 22.90 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.149.149 listed in list.dnswl.org] Cc: Rabin Vincent , Srinidhi Kasagar , Catalin Marinas , Linus Walleij , Will Deacon , Lee Jones , Adrian Bunk , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sun, 04 Sep 2011 10:14:39 +0000 (UTC) On Sunday 04 September 2011 02:31 PM, Linus Walleij wrote: > From: Linus Walleij > > Fighting unfixed U-Boots and other beasts that may the cache in > a locked-down state when starting the kernel, we make sure to > disable all cache lock-down when initializing the l2x0 so we > are in a known state. > > Cc: Srinidhi Kasagar > Cc: Rabin Vincent > Cc: Adrian Bunk > Cc: Rob Herring > Cc: Catalin Marinas > Cc: Will Deacon > Reported-by: Jan Rinze > Tested-by: Robert Marklund > Signed-off-by: Linus Walleij > --- > arch/arm/mm/cache-l2x0.c | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c > index 44c0867..b03c835 100644 > --- a/arch/arm/mm/cache-l2x0.c > +++ b/arch/arm/mm/cache-l2x0.c > @@ -338,6 +338,10 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) > writel_relaxed(1, l2x0_base + L2X0_CTRL); > } > > + /* Make sure that I&D is not locked down when starting */ > + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D); > + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I); > + Few points on this patch Linus W. 1. You should do above before enabling the L2X0, so you need to move this up. 2. You are taking care of only one master. i.e CPU0. You need to do that for CPU1 and if there are more than two CPU's, then for them too. 3. Even after taking care of 1 and 2, the arch, which enable L2X0 controller using secure API,s would have already enabled L2X0, so they need to do the above in arch code to be effective and correct. That should be fine though. At least for you intended change below change should do. It's taking care of only two CPUs though. Regards Santosh * If you are booting from non-secure mode diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 16bd480..e04e947 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -45,8 +45,10 @@ #define L2X0_CLEAN_INV_LINE_PA 0x7F0 #define L2X0_CLEAN_INV_LINE_IDX 0x7F8 #define L2X0_CLEAN_INV_WAY 0x7FC -#define L2X0_LOCKDOWN_WAY_D 0x900 -#define L2X0_LOCKDOWN_WAY_I 0x904 +#define L2X0_LOCKDOWN_WAY_D0 0x900 +#define L2X0_LOCKDOWN_WAY_D1 0x908 +#define L2X0_LOCKDOWN_WAY_I0 0x904 +#define L2X0_LOCKDOWN_WAY_I1 0x90C #define L2X0_TEST_OPERATION 0xF00 #define L2X0_LINE_DATA 0xF10 #define L2X0_LINE_TAG 0xF30 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 44c0867..f95b269 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -322,6 +322,12 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) way_size = 1 << (way_size + 3); l2x0_size = ways * way_size * SZ_1K; + /* Clear the I and D lock-down way registers */ + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D0); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D1); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I0); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I1); + /* * Check if l2x0 controller is already enabled.