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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ooCmZuvrf2Gm4bICFFXYpnG/ykOljhI+a/Wvr3/YrU31TqNEcJswU4/eeeHK+MVYect1TQdbfYR+el9X/h9H3socayLF93iXdeSQygy9fCHc2E/Ki8u2sGgh05TTz5gV3oGhqWrVNuLBK2OmFjHv2mbqBfvtEkRTgm/eHzN9ieFKWLuElW8chjVBPylEB5u17CTwWiJLzQzWGfkcLvX1TeI1fE0hu2P/P/U9kwKm4R3rfEo+pwXJisA4A8tWu4woUa1TEWbhL/ly1FpKmEZkMe0/0aerAjXZ8kDDN1LxpiTp/8vQil6YaEs3j4K0BP8klR7jlyl8ojXdlOiaV5rugzMn2voX40bxlWS3SeJoarSg7PNwFCJB2NohX2ebdDBHORzgWybfEMrDHDPkleZuHDIRffylLutQRYzavgUvUL7gA87Li21J7Ty6DdP/hwtwmpkfKo27jdalk4GKa1oFvKp73UkU2hu4QU6w6bFdiZ/0lYVlaqHu3BEo5ipD+VToEoTVelIZEZL12V6b1CrQqSpIOihZNK3mDdXYbQZufzWzzrzgLxVlTRn2JiiGmHenmuifjIfl6oXevDcYu6nc1meimJr9pszGo2r41FvojAN7y0e4bCI/F7EDNgVj2hxIePgIpri1nenVAo0i1o+ofgcVH3o/m520jPWgspWY7NbY0ysYryYQ6TTxBz1wqkSlQexlo1rzUbP40G16Qnl0loZO0hvruVpZFxIzfpy0HQe+B5TnUIiLmME5+BYWPMa4gNB5IkuHIoe0sxR0ekLrGIqgivVvPDZb3Bq5XpgMDujeSGrvEXEKDrRunmFAtHSRwPwNbewrTh87NG86oF58Nfjh5c3Mt3bvC7Qz2xCm16yNOIhrnq8avp05Z72G2wTAtMD/8lWCAA9YmqD1iRq288CCsxgBBf9g3f/V3PSUnaPyyPxMCoLzUorAhQx9FADolND51q8Sy8F7cH6LF2x5Rq7rDLfMDt5b12UUzStc71tX5wR2lzliIdInjSXOlzhFihjHNBjv4ti2PX6z2MzReO+HcCoyr7K/Lx7o8DmbVIXpxUOvUXx4vF3grFfru+V+hHfyTIErItZfXYRjbgerj6h1wFeglzZBD0RCZlU0INBaDTkDK7SNn9Egyl7X/iM7klF5SkoxWp5RRZTX5BBhSjZC1tXAGWHxpLL9bdJ58QeUc2SxI7tgAbxxIwZuQwKy/EfCHF44u4Sev95BnkabtAM1sBbStzXH4ae3kB0BThIYsT16J9equ7ZS83YVqfRDKvlTu+yh3H/8OQl7gMx+SQVSAt/SXLvfr70N8C3bPnzunXxPmbc2c0z02qmFyo9Wkis2KQsOB95ug+RE566lK8TstOQ3LsgrOgnL9z4sc6HS6KrUhuuiPHMXshDKpQQFYUIpd6SKCf0lR6qnxvA2cwDlDvDYqk6CuAUK15ZpAb0SakXF4xgvVhEFtEq0BPlGslVA7JYHR3aa7NgC4Jbnv0cEfyIxzJfYqTvbTfqM3C5cVFB3z0UKCCPGD5k6ckj5ETtbqNHNC70PmYbM3Xww2MYgVk2uzHofNxdjuWACPNSa9LpjLGmHHdKmH47Z94Csw9zuRN1RZcbnLKAt4SdxhIcjlII6wGCq6Hoog1WnAOxZPowyIGFd4pxllyi75hm5 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8aae7947-98f3-4f1e-b9fa-08db1e074088 X-MS-Exchange-CrossTenant-AuthSource: SA1PR01MB8062.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2023 05:54:30.0457 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GKX2PRustEDNR2xAi+IXYF7Y7J+mP1NImmvlPm8bm/I6HcmyQBmdedUrTzdJ2gXeyCRhBmZIi8/1rWbDkpMYFpfzVJ4FzF/TZepiLWxBdr8spbTPw+cLncfiEQPB9I/B X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR01MB6460 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230305_215440_108945_DE369967 X-CRM114-Status: GOOD ( 12.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An Ampere Computing design decision to not support 64-bit read/write access in the ETMv4.6 implementation. The Ampere work around is to split ETMv4.6 64-bit register access into 2 ea. 32-bit read/write accesses. AC03_DEBUG_10 is described in the AmpereOne Developer Errata document: https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-device-documentation Signed-off-by: Steve Clevenger --- drivers/hwtracing/coresight/coresight-etm4x.h | 58 ++++++++++++++----- 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 434f4e95ee17..17457ec71876 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -539,11 +539,6 @@ readl_relaxed((csa)->base + (offset)) : \ read_etm4x_sysreg_offset((offset), false))) -#define etm4x_relaxed_read64(csa, offset) \ - ((u64)((csa)->io_mem ? \ - readq_relaxed((csa)->base + (offset)) : \ - read_etm4x_sysreg_offset((offset), true))) - #define etm4x_read32(csa, offset) \ ({ \ u32 __val = etm4x_relaxed_read32((csa), (offset)); \ @@ -567,15 +562,6 @@ false); \ } while (0) -#define etm4x_relaxed_write64(csa, val, offset) \ - do { \ - if ((csa)->io_mem) \ - writeq_relaxed((val), (csa)->base + (offset)); \ - else \ - write_etm4x_sysreg_offset((val), (offset), \ - true); \ - } while (0) - #define etm4x_write32(csa, val, offset) \ do { \ __io_bw(); \ @@ -1091,6 +1077,50 @@ void etm4_config_trace_mode(struct etmv4_config *config); u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); +/* 64-bit aligned to convert 64-bit access to 2 ea. 32-bit access */ +#pragma pack(push, 8) + +struct etm_quad_split { + u32 lsw; + u32 msw; +}; + +#pragma pack(pop) + +static inline u64 etm4x_relaxed_read64(struct csdev_access *csa, unsigned int offset) +{ + if (csa->io_mem) { + if (csa->no_quad_mmio) { + /* split 64-bit reads into 2 consecutive 32-bit reads */ + struct etm_quad_split container; + + container.lsw = etm4x_read32(csa, offset); + container.msw = etm4x_read32(csa, offset + sizeof(u32)); + + return *(u64 *) &container; + } else + return readq_relaxed(csa->base + offset); + } else + return read_etm4x_sysreg_offset(offset, true); +} + +static inline void etm4x_relaxed_write64(struct csdev_access *csa, u64 quad, unsigned int offset) +{ + if (csa->io_mem) { + /* split 64-bit writes into 2 consecutive 32-bit writes */ + if (csa->no_quad_mmio) { + struct etm_quad_split container; + + *(u64 *) &container = quad; + + etm4x_relaxed_write32(csa, container.lsw, offset); + etm4x_relaxed_write32(csa, container.msw, offset + sizeof(u32)); + } else + writeq_relaxed(quad, csa->base + offset); + } else + write_etm4x_sysreg_offset(quad, offset, true); \ +} + static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) { return drvdata->arch >= ETM_ARCH_ETE;