| Message ID | 4f43a337677572fbf2b2c8e27152db426e024f7a.1445146992.git.maitysanchayan@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Ping? On 15-10-18 11:18:48, Sanchayan Maity wrote: > Something seems to have gone wrong during the merging of the device > tree changes with the following patch > > "ARM: dts: add property for maximum ADC clock frequencies" > > The property "fsl,adck-max-frequency" instead of being applied for > the ADC1 node got applied to the esdhc0 node. This patch fixes it. > > Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> > --- > arch/arm/boot/dts/vfxxx.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi > index 6736bae..a64bfe1 100644 > --- a/arch/arm/boot/dts/vfxxx.dtsi > +++ b/arch/arm/boot/dts/vfxxx.dtsi > @@ -461,6 +461,8 @@ > clock-names = "adc"; > #io-channel-cells = <1>; > status = "disabled"; > + fsl,adck-max-frequency = <30000000>, <40000000>, > + <20000000>; > }; > > esdhc0: esdhc@400b1000 { > @@ -472,8 +474,6 @@ > <&clks VF610_CLK_ESDHC0>; > clock-names = "ipg", "ahb", "per"; > status = "disabled"; > - fsl,adck-max-frequency = <30000000>, <40000000>, > - <20000000>; > }; > > esdhc1: esdhc@400b2000 { > -- > 2.6.1 >
On Sun, Oct 18, 2015 at 11:18:48AM +0530, Sanchayan Maity wrote: > Something seems to have gone wrong during the merging of the device > tree changes with the following patch > > "ARM: dts: add property for maximum ADC clock frequencies" > > The property "fsl,adck-max-frequency" instead of being applied for > the ADC1 node got applied to the esdhc0 node. This patch fixes it. > > Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Oops, sorry. Applied it. Shawn
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 6736bae..a64bfe1 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -461,6 +461,8 @@ clock-names = "adc"; #io-channel-cells = <1>; status = "disabled"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; }; esdhc0: esdhc@400b1000 { @@ -472,8 +474,6 @@ <&clks VF610_CLK_ESDHC0>; clock-names = "ipg", "ahb", "per"; status = "disabled"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; }; esdhc1: esdhc@400b2000 {
Something seems to have gone wrong during the merging of the device tree changes with the following patch "ARM: dts: add property for maximum ADC clock frequencies" The property "fsl,adck-max-frequency" instead of being applied for the ADC1 node got applied to the esdhc0 node. This patch fixes it. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> --- arch/arm/boot/dts/vfxxx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)