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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: F7iQzQHfhiqxMPAEC08HVhWSQ45JiU5nBttlIcCpQdKjaeWGLSXzKQlqYRsbYkPdG41JWVm+podsSTUTylX3OT2gXlKRwUqHThqcqe7W8Mok5HaoB2+24dBXQyZAkr2y2IEMXEgaotsxNpkBrm2rt5WbVmdTqXMxqNk1ApPS6dHENMPLnF1NI5zybvH5nlBKJKxQivabeFIuwLWo2EoUjC2YL5HkKotVs2r0gjUplClI2RcSGsde63mRIo2Xq+sQpU9ybwQ5FpM8lJi2Fv2fkYwvfGdlKbOXQZRtOZMjAvbsfJ+wATqP9QhdjhCVwIMEa9cqWE4682E+APnpUE8OtPw77jIehiUK5gPGFQY2bZlELqWrxIv8MYhSWHNElGX8TwTaYrsWtieM1ffuz5UVSFQX8MJxob69ZOWm5QVAMqZzXapHTqJp+Yf1/dhWxH8fnLhwqZGxtak+Qrcq/CZ9+HB7uz+DdqmOMAd++88wXqzetbRrsAmEoITH3swfdQ/ABGBTSjKTjylmmfYMeIV7Gwgvp3R68Ccf4hbfwcY9haVIbhXEqHpCp3jaMeTVKty3+W5PS5yDcTnhCD5pkkR1RtZx0yI9IZ0eSdkYgGuyl7C1SK9nsysm2+/g+0dsX4fAnvTA4glPaLSStl+7cco86MVjv1pCpUHKgztPyWTya+QOXXzZfV1HguHWfpjgkmqJLpPzo5cBFmyvpKu3SjSs/OufM4uYyB3A4pZhp9It15TR0fabNccLkN1aIMUMtM4DZKMGuGk/H7E55PAE9RV4BTCSzEGLUWmHiXFsSW1xiBUybAlsnMqYIQN64Ppz473QOu+JNe9f2Yr6lTm1p2LGM4+J8dNDUCDW05UHkpKYbIT2hjctMla0+F1ACY+aMBz/CTKZ11dQLy6qmF5spyjQpZcFhSJ91LESvfoSuzw1/giDVojGTz+/NO9ICWU1lywGZpXcw/VOvLKm+GDF7hMuKTnRsyBq/eTctsZ1+bgboc9trOS9f3JvulVzPutFZwPBNxUEXCmKQ0wHkONIhVwR3tbA1BFwI1fIIAf+sqi24J/+18L9jYdUz54L4ZxOPvUvh4b9sFCSTT2sJL/J90aHdf/vJ2evVRkj5hwoz7zxLxjoW6RMl1alvOKkar88fGQG2PgfqdF4LD24G19QQ28divt6JHT6FBjehfJzcP74ajVYe9gS3g2YtTa+TLUBUGTNrtQZVUsJwRhyGZIYUAFNkuFApg6Exr9Nb+9g9WkPvgYnv/4lYQnlHeoNjSmo9kDreGrAN90+007n8dHj01LM9uR6t910+EisMDd8uDjMjAsBlxqbejATy9yHIHroFQX9sY83jRgiLAQ5OIxN4D9FyyHAfk7BFaOlqQx0yrNLsjyAIVD9TJvlxenBBO53zJiJGC6y9GLCSBklnv1AuEeYJPBucRpr4k1D6EldRUhLJFJ359TU0EuS25bq1DoABKrEbKR30/yfMDY4bRHDejD31dYZeUtYx7dH2tl/1ombR58NKYwpBhJkWJu2ZhzF9jM30PhH5n0QQExZoltIIE+rxOLB3mK9Qsv76jXYAURKk1AYoJUV12o74Wkn+V9XoTTHXHb37+HlFik9VzTyBZYUJaDGf8qQHndZ1D0bh4ih+EHpODXaLZsO1zqwUOcuRMTl X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e645809-866c-4df2-e4dd-08db2045805f X-MS-Exchange-CrossTenant-AuthSource: SA1PR01MB8062.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 02:25:08.3063 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NM1F+H5hEF66u1XGT1CKF4GCqFilw/UsiirGaIBTL8SlBTE8/51o7fLVbsmpTpEh3I0xIVJtYhJURJjn1zHSjnFFA6PI9b0GcBJPKjXqi3tdqSr7XNKLRnPFiGhUkws6 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR01MB6846 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_182515_625752_ADD393D0 X-CRM114-Status: GOOD ( 13.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An Ampere Computing design decision to not support 64-bit read/write access in the ETMv4.6 implementation. The Ampere work around is to split ETMv4.6 64-bit register access into 2 ea. 32-bit read/write accesses. AC03_DEBUG_10 is described in the AmpereOne Developer Errata document: https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-device-documentation Changes since v2: Removed errant '\' character from end of line 1121 in coresight-etm4x.h. Signed-off-by: Steve Clevenger --- drivers/hwtracing/coresight/coresight-etm4x.h | 58 ++++++++++++++----- 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 434f4e95ee17..992154770556 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -539,11 +539,6 @@ readl_relaxed((csa)->base + (offset)) : \ read_etm4x_sysreg_offset((offset), false))) -#define etm4x_relaxed_read64(csa, offset) \ - ((u64)((csa)->io_mem ? \ - readq_relaxed((csa)->base + (offset)) : \ - read_etm4x_sysreg_offset((offset), true))) - #define etm4x_read32(csa, offset) \ ({ \ u32 __val = etm4x_relaxed_read32((csa), (offset)); \ @@ -567,15 +562,6 @@ false); \ } while (0) -#define etm4x_relaxed_write64(csa, val, offset) \ - do { \ - if ((csa)->io_mem) \ - writeq_relaxed((val), (csa)->base + (offset)); \ - else \ - write_etm4x_sysreg_offset((val), (offset), \ - true); \ - } while (0) - #define etm4x_write32(csa, val, offset) \ do { \ __io_bw(); \ @@ -1091,6 +1077,50 @@ void etm4_config_trace_mode(struct etmv4_config *config); u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); +/* 64-bit aligned to convert 64-bit access to 2 ea. 32-bit access */ +#pragma pack(push, 8) + +struct etm_quad_split { + u32 lsw; + u32 msw; +}; + +#pragma pack(pop) + +static inline u64 etm4x_relaxed_read64(struct csdev_access *csa, unsigned int offset) +{ + if (csa->io_mem) { + if (csa->no_quad_mmio) { + /* split 64-bit reads into 2 consecutive 32-bit reads */ + struct etm_quad_split container; + + container.lsw = etm4x_read32(csa, offset); + container.msw = etm4x_read32(csa, offset + sizeof(u32)); + + return *(u64 *) &container; + } else + return readq_relaxed(csa->base + offset); + } else + return read_etm4x_sysreg_offset(offset, true); +} + +static inline void etm4x_relaxed_write64(struct csdev_access *csa, u64 quad, unsigned int offset) +{ + if (csa->io_mem) { + /* split 64-bit writes into 2 consecutive 32-bit writes */ + if (csa->no_quad_mmio) { + struct etm_quad_split container; + + *(u64 *) &container = quad; + + etm4x_relaxed_write32(csa, container.lsw, offset); + etm4x_relaxed_write32(csa, container.msw, offset + sizeof(u32)); + } else + writeq_relaxed(quad, csa->base + offset); + } else + write_etm4x_sysreg_offset(quad, offset, true); +} + static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) { return drvdata->arch >= ETM_ARCH_ETE;