From patchwork Mon Sep 3 16:20:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 1400461 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 9FF1EDF280 for ; Mon, 3 Sep 2012 16:24:16 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T8ZOc-0007we-C6; Mon, 03 Sep 2012 16:21:06 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T8ZOY-0007wB-N0 for linux-arm-kernel@lists.infradead.org; Mon, 03 Sep 2012 16:21:03 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q83GL0or010344; Mon, 3 Sep 2012 11:21:00 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q83GL01V002640; Mon, 3 Sep 2012 11:21:00 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Mon, 3 Sep 2012 11:20:59 -0500 Received: from [137.167.124.35] (una0919096.tif.ti.com [137.167.124.35]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q83GKwmA005706; Mon, 3 Sep 2012 11:20:59 -0500 Message-ID: <5044D8E5.5010705@ti.com> Date: Mon, 3 Sep 2012 18:20:53 +0200 From: Benoit Cousson Organization: Texas Instruments User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120714 Thunderbird/14.0 MIME-Version: 1.0 To: "tony@atomide.com" Subject: [PATCH] ARM: dts: OMAP4: Cleanup and move GIC outside of the OCP node X-Spam-Note: CRM114 invocation failed X-Spam-Score: -7.1 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.2 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "devicetree-discuss@lists.ozlabs.org" , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Remove a useless comment and move GIC controller outside of the OCP node since it does use the MPU internal bus and not the OCP. This will not change the functionality but will reflect the reality more accurately. Signed-off-by: Benoit Cousson Acked-by: Santosh Shilimkar --- Hi Tony This is a minor cleanup done since Santosh's series is introducing some more MPU devices that does not belong to the TI main OCP interconnect. It makes sense for consistency / accuracy to move GIC to the same location. Regards, Benoit arch/arm/boot/dts/omap4.dtsi | 40 ++++++++-------------------------------- 1 files changed, 8 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2b670ab..1853dc7 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -38,6 +38,14 @@ }; }; + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + }; + L2: l2-cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; @@ -76,30 +84,6 @@ /* * XXX: Use a flat representation of the OMAP4 interconnect. * The real OMAP interconnect network is quite complex. - * - * MPU -+-- MPU_PRIVATE - GIC, L2 - * | - * +----------------+----------+ - * | | | - * + +- EMIF - DDR | - * | | | - * | + +--------+ - * | | | - * | +- L4_ABE - AESS, MCBSP, TIMERs... - * | | - * +- L3_MAIN --+- L4_CORE - IPs... - * | - * +- L4_PER - IPs... - * | - * +- L4_CFG -+- L4_WKUP - IPs... - * | | - * | +- IPs... - * +- IPU ----+ - * | | - * +- DSP ----+ - * | | - * +- DSS ----+ - * * Since that will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. @@ -111,14 +95,6 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - }; - gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1";