From patchwork Mon Nov 5 17:44:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 1699901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 9E1883FCA5 for ; Mon, 5 Nov 2012 17:47:18 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TVQjO-0006SS-8Y; Mon, 05 Nov 2012 17:45:02 +0000 Received: from mail-ob0-f177.google.com ([209.85.214.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TVQjI-0006RD-Fj for linux-arm-kernel@lists.infradead.org; Mon, 05 Nov 2012 17:44:59 +0000 Received: by mail-ob0-f177.google.com with SMTP id wd20so5749943obb.36 for ; Mon, 05 Nov 2012 09:44:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=Tu8VpzRG2t3k1OW6zqALMzwxJx6HrPDgvXzvlLjjgJM=; b=KFOYYc7nPOGFnJZuMyLQJxDYOrX7rn5OeT5y8QVGZzSxcZBz8nuVPou/aQth02eY1k j95soQRqZ7FMPAnxCt4YWwxBa45i2VRiSVqPsAQ0iQMki5vXNi9s8O7/Far0qHpXr0Rf GCYpYIZPn7sHEvYgEJ7/4yvbPtJFXvBfMrPRt9aUq7zhM7F6iQZCzLDfVzMK4M3ZFKf2 r0FqGiPBYIInPvwEyEtveEnnvWKM1oqp30234bF3LfIjRjsQ56OYKal+PrLCKOug+0P7 N1TesMw0hTf7eachqG9VPZb6l4igORJI8GZpWwCX5W4UotL3Eg2h6WRmP7++99rKDTqy qRNg== Received: by 10.182.86.225 with SMTP id s1mr8338952obz.91.1352137495183; Mon, 05 Nov 2012 09:44:55 -0800 (PST) Received: from [10.10.10.90] ([173.226.190.126]) by mx.google.com with ESMTPS id a7sm18271611obw.6.2012.11.05.09.44.53 (version=SSLv3 cipher=OTHER); Mon, 05 Nov 2012 09:44:54 -0800 (PST) Message-ID: <5097FB14.20404@gmail.com> Date: Mon, 05 Nov 2012 11:44:52 -0600 From: Rob Herring User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: Dave Martin Subject: Re: [PATCH] ARM: decompressor: clear SCTLR.A bit for v7 cores References: <20121025093411.GA32662@sig21.net> <50893389.2090002@gmail.com> <20121025141645.GA16962@sig21.net> <50894BC2.5050706@gmail.com> <20121025150816.GA3874@sig21.net> <20121105104839.GA2005@linaro.org> <20121105111346.GF28327@n2100.arm.linux.org.uk> <20121105130255.GD2005@linaro.org> <20121105153917.GG28327@n2100.arm.linux.org.uk> <20121105172624.GE2005@linaro.org> In-Reply-To: <20121105172624.GE2005@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121105_124456_740825_C136495C X-CRM114-Status: GOOD ( 22.78 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (robherring2[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (robherring2[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Nicolas Pitre , Johannes Stezenbach , Russell King - ARM Linux , Arnd Bergmann , Olof Johansson , Shawn Guo , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On 11/05/2012 11:26 AM, Dave Martin wrote: > On Mon, Nov 05, 2012 at 11:13:51AM -0500, Nicolas Pitre wrote: >> On Mon, 5 Nov 2012, Russell King - ARM Linux wrote: >> >>> On Mon, Nov 05, 2012 at 01:02:55PM +0000, Dave Martin wrote: >>>> Why not allow unaligned accesses in the decompressor, though, both >>>> for v6 and v7? >>> >>> EXACTLY. >> >> I have no objections to that. In fact, I made a remark to this effect >> in my initial review of this patch. Whether or not gcc does take >> advantage of this hardware ability in the end is orthogonal. > > For the sake of argument, here's how it might look. > > Currently, I make no attempt to restore the original state of the U bit. > The A bit if forced later by the kernel during boot, after a short window > during which we should only run low-level arch code and therefore where > no unaligned accesses should happen. > > Does anyone think these issues are likely to be important? > And here is my updated version that does v6 somewhat differently: 8<------------------------------------------------------------------ From 76c2b7685397f13aa53f426822128430fc24b8a0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 5 Nov 2012 11:39:48 -0600 Subject: [PATCH v2] ARM: decompressor: clear SCTLR.A bit for v6 and v7 cores With recent compilers and move to generic unaligned.h in commit d25c881 (ARM: 7493/1: use generic unaligned.h), unaligned accesses will be used by the LZO decompressor on v7 cores. So we need to make sure unaligned accesses are allowed by clearing the SCTLR A bit. While v6 can support unaligned accesses, it is optional and current compilers won't emit unaligned accesses. In case this changes and to align with the kernel behavior, we clear the A bit and set the U bit. Signed-off-by: Rob Herring Acked-by: Nicolas Pitre Tested-by: Shawn Guo --- arch/arm/boot/compressed/head.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index bc67cbf..f14d7ec 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -629,6 +629,11 @@ __armv4_mmu_cache_on: mcr p15, 0, r0, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs mrc p15, 0, r0, c1, c0, 0 @ read control reg + mrc p15, 0, r11, c0, c0 @ get processor ID + and r11, r11, #0xf0000 + tst r11, #0x70000 @ ARMv6 + orreq r0, r0, #1 << 22 @ set SCTLR.U + biceq r0, r0, #1 << 1 @ clear SCTLR.A orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x0030 #ifdef CONFIG_CPU_ENDIAN_BE8 @@ -654,6 +659,7 @@ __armv7_mmu_cache_on: #endif mrc p15, 0, r0, c1, c0, 0 @ read control reg bic r0, r0, #1 << 28 @ clear SCTLR.TRE + bic r0, r0, #1 << 1 @ clear SCTLR.A orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer #ifdef CONFIG_MMU