diff mbox

ARM big-endian on current kernels for linux-3.8

Message ID 511A7B14.1020107@codethink.co.uk (mailing list archive)
State New, archived
Headers show

Commit Message

Ben Dooks Feb. 12, 2013, 5:25 p.m. UTC 
On 12/02/13 17:08, Thomas Petazzoni wrote:
> Dear Ben Dooks,
>
> On Fri,  8 Feb 2013 23:17:30 +0000, Ben Dooks wrote:
>> I have been working on getting big-endian kernels working, mainly from
>> little-endian boot envrionments. The following patch series is what I
>> have been working on, mainly on the highbank and axp systems.
>
> Nice!
>
>> Feedback and testing is welcome.
>
> I've tested your patch set on Armada XP. The kernel boots fine, but it
> fails to bring up the secondary CPUs:

Yes, missed updating the coherency_ll.S patch.

Attached new patch

Comments

Thomas Petazzoni Feb. 12, 2013, 6:49 p.m. UTC | #1 
Dear Ben Dooks,

On Tue, 12 Feb 2013 17:25:40 +0000, Ben Dooks wrote:

> >> Feedback and testing is welcome.
> >
> > I've tested your patch set on Armada XP. The kernel boots fine, but
> > it fails to bring up the secondary CPUs:
> 
> Yes, missed updating the coherency_ll.S patch.
> 
> Attached new patch

Thanks, I'll test this one tomorrow. Any pointer for a known-working
armeb toolchain?

Thanks,

Thomas
Ben Dooks Feb. 12, 2013, 6:54 p.m. UTC | #2 
On 12/02/13 18:49, Thomas Petazzoni wrote:
> Dear Ben Dooks,
>
> On Tue, 12 Feb 2013 17:25:40 +0000, Ben Dooks wrote:
>
>>>> Feedback and testing is welcome.
>>>
>>> I've tested your patch set on Armada XP. The kernel boots fine, but
>>> it fails to bring up the secondary CPUs:
>>
>> Yes, missed updating the coherency_ll.S patch.
>>
>> Attached new patch
>
> Thanks, I'll test this one tomorrow. Any pointer for a known-working
> armeb toolchain?

I've been building with gcc 4.6.3
diff mbox

Patch

commit 21d31d4d4667b93e2070e7516ca7b9f9b7c72d42
Author: Ben Dooks <ben.dooks@codethink.co.uk>
Date:   Fri Feb 1 10:36:22 2013 +0000

    mvebu: support running big-endian
    
    Add indication we can run these cores in BE mode, and ensure that the
    secondary CPU is set to big-endian mode in the initialisation code as
    the initial code runs little-endian.
    
    Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13e..2afa026 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,5 +1,6 @@ 
 config ARCH_MVEBU
 	bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select CLKSRC_MMIO
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391..af48c95 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -20,6 +20,8 @@ 
 #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
 
+#include <asm/assembler.h>
+
 	.text
 /*
  * r0: Coherency fabric base register address
@@ -29,6 +31,7 @@  ENTRY(ll_set_cpu_coherent)
 	/* Create bit by cpu index */
 	mov	r3, #(1 << 24)
 	lsl	r1, r3, r1
+ARM_BE(	rev	r1, r1)
 
 	/* Add CPU to SMP group - Atomic */
 	add	r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ed..8b09f8d 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -36,6 +36,10 @@ 
  */
 ENTRY(armada_xp_secondary_startup)
 
+#ifdef CONFIG_CPU_BE8_BOOT_LE
+	setend	be
+#endif
+
 	/* Read CPU id */
 	mrc     p15, 0, r1, c0, c0, 5
 	and     r1, r1, #0xF