From patchwork Tue Feb 12 17:25:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 2130201 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 3F8E3DFB7B for ; Tue, 12 Feb 2013 17:28:06 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U5Jc1-0003kZ-CX; Tue, 12 Feb 2013 17:25:45 +0000 Received: from ducie-dc1.codethink.co.uk ([37.128.190.40]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U5Jby-0003iy-O7 for linux-arm-kernel@lists.infradead.org; Tue, 12 Feb 2013 17:25:43 +0000 Received: by ducie-dc1.codethink.co.uk (Postfix, from userid 1002) id E4EE846C18C; Tue, 12 Feb 2013 17:25:39 +0000 (GMT) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on ducie-dc1.codethink.co.uk X-Spam-Level: X-Spam-Status: No, score=-2.9 required=6.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.2 Received: from [192.168.24.216] (rainbowdash.dyn.ducie.codethink.co.uk [192.168.24.216]) by ducie-dc1.codethink.co.uk (Postfix) with ESMTPSA id 6C047463517; Tue, 12 Feb 2013 17:25:39 +0000 (GMT) Message-ID: <511A7B14.1020107@codethink.co.uk> Date: Tue, 12 Feb 2013 17:25:40 +0000 From: Ben Dooks Organization: Codethink Limited. User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130116 Icedove/10.0.12 MIME-Version: 1.0 To: Thomas Petazzoni Subject: Re: ARM big-endian on current kernels for linux-3.8 References: <1360365467-25056-1-git-send-email-ben.dooks@codethink.co.uk> <20130212180858.289c3efa@skate> In-Reply-To: <20130212180858.289c3efa@skate> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130212_122542_976211_7304A1DE X-CRM114-Status: GOOD ( 14.67 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: =?ISO-8859-1?Q?Gregory_Cl=E9m?= =?ISO-8859-1?Q?ent?= , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On 12/02/13 17:08, Thomas Petazzoni wrote: > Dear Ben Dooks, > > On Fri, 8 Feb 2013 23:17:30 +0000, Ben Dooks wrote: >> I have been working on getting big-endian kernels working, mainly from >> little-endian boot envrionments. The following patch series is what I >> have been working on, mainly on the highbank and axp systems. > > Nice! > >> Feedback and testing is welcome. > > I've tested your patch set on Armada XP. The kernel boots fine, but it > fails to bring up the secondary CPUs: Yes, missed updating the coherency_ll.S patch. Attached new patch commit 21d31d4d4667b93e2070e7516ca7b9f9b7c72d42 Author: Ben Dooks Date: Fri Feb 1 10:36:22 2013 +0000 mvebu: support running big-endian Add indication we can run these cores in BE mode, and ensure that the secondary CPU is set to big-endian mode in the initialisation code as the initial code runs little-endian. Signed-off-by: Ben Dooks diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 440b13e..2afa026 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,5 +1,6 @@ config ARCH_MVEBU bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 + select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select COMMON_CLK select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index 53e8391..af48c95 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -20,6 +20,8 @@ #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4 +#include + .text /* * r0: Coherency fabric base register address @@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent) /* Create bit by cpu index */ mov r3, #(1 << 24) lsl r1, r3, r1 +ARM_BE( rev r1, r1) /* Add CPU to SMP group - Atomic */ add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index a06e0ed..8b09f8d 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -36,6 +36,10 @@ */ ENTRY(armada_xp_secondary_startup) +#ifdef CONFIG_CPU_BE8_BOOT_LE + setend be +#endif + /* Read CPU id */ mrc p15, 0, r1, c0, c0, 5 and r1, r1, #0xF