From patchwork Mon Jun 17 22:20:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 2737831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 176DEC0AB1 for ; Mon, 17 Jun 2013 22:21:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 20EF520146 for ; Mon, 17 Jun 2013 22:21:21 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BDFF020169 for ; Mon, 17 Jun 2013 22:21:19 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UohnE-0000Pz-Rj; Mon, 17 Jun 2013 22:20:57 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uohn7-0006Xb-T3; Mon, 17 Jun 2013 22:20:49 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uohn2-0006UV-32 for linux-arm-kernel@lists.infradead.org; Mon, 17 Jun 2013 22:20:45 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r5HMKFQl015017; Mon, 17 Jun 2013 17:20:15 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r5HMKFxw026688; Mon, 17 Jun 2013 17:20:15 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Mon, 17 Jun 2013 17:20:15 -0500 Received: from [158.218.103.117] (ula0393909.am.dhcp.ti.com [158.218.103.117]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r5HMKE3T014383; Mon, 17 Jun 2013 17:20:14 -0500 Message-ID: <51BF8B9E.8080405@ti.com> Date: Mon, 17 Jun 2013 18:20:14 -0400 From: Santosh Shilimkar User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Olof Johansson Subject: Re: [PATCH v2 1/3] ARM: dts: keystone: Add minimal Keystone SOC device tree data References: <1371072317-15030-1-git-send-email-santosh.shilimkar@ti.com> <1371072317-15030-2-git-send-email-santosh.shilimkar@ti.com> <20130617211252.GH28497@quad.lixom.net> In-Reply-To: <20130617211252.GH28497@quad.lixom.net> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130617_182044_225500_9A4921AF X-CRM114-Status: GOOD ( 17.96 ) X-Spam-Score: -8.0 (--------) Cc: Grant Likely , arm@kernel.org, linux-arm-kernel@lists.infradead.org, arnd@arndb.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Monday 17 June 2013 05:12 PM, Olof Johansson wrote: > Hi, > > Sorry for the somewhat delayed review of this. I've got some nitpicks below, > they should be easy to fix and respin. > > Since they are just nits, feel free to add: > > Acked-by: Olof Johansson > > when corrected. > Thanks Olof. For record, updated patch below with your ack added. Regards, Santosh From 35cdbdca30652c615340373bef6e708a74e67c8b Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 10 Jun 2013 11:33:31 -0400 Subject: [PATCH 1/3] ARM: dts: keystone: Add minimal Keystone SOC device tree data Add minimal device tree data for Keystone2 based SOCs. Patch contains mainly ARM related SOC data and nothing about EVM specific yet. Cc: Grant Likely Cc: Arnd Bergmann Cc: arm@kernel.org Acked-by: Olof Johansson Signed-off-by: Santosh Shilimkar --- .../devicetree/bindings/arm/keystone/keystone.txt | 10 ++ arch/arm/boot/dts/keystone.dts | 117 ++++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/keystone/keystone.txt create mode 100644 arch/arm/boot/dts/keystone.dts diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt new file mode 100644 index 0000000..231e031 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keystone/keystone.txt @@ -0,0 +1,10 @@ +TI Kesytone Platforms Device Tree Bindings +----------------------------------------------- + +Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the +following properties. + +Required properties: + - compatible: All TI specific devices present in Keystone SOC should be in + the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 + type UART should use the specified compatible for those devices. diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts new file mode 100644 index 0000000..1334b42 --- /dev/null +++ b/arch/arm/boot/dts/keystone.dts @@ -0,0 +1,117 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "Texas Instruments Keystone 2 SoC"; + compatible = "ti,keystone-evm"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + memory { + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0x308>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 20 0xf01>, + <0 21 0xf01>, + <0 22 0xf01>, + <0 23 0xf01>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0x0 0xc0000000>; + + rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + reg = <0x023100e8 4>; /* pll reset control reg */ + }; + + uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clock-frequency = <133120000>; + interrupts = <0 277 0xf01>; + }; + + uart1: serial@02531000 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + clock-frequency = <133120000>; + interrupts = <0 280 0xf01>; + }; + + }; +};