From patchwork Mon Sep 23 11:11:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 2927581 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 215BDBFF05 for ; Mon, 23 Sep 2013 11:12:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6D41120395 for ; Mon, 23 Sep 2013 11:12:46 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E222620115 for ; Mon, 23 Sep 2013 11:12:40 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VO448-0001je-6A; Mon, 23 Sep 2013 11:12:32 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VO445-00033Y-Oo; Mon, 23 Sep 2013 11:12:29 +0000 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VO441-000329-FB for linux-arm-kernel@lists.infradead.org; Mon, 23 Sep 2013 11:12:26 +0000 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.14.5/8.14.5) with SMTP id r8NBBuNQ031568; Mon, 23 Sep 2013 04:11:56 -0700 Received: from sc-owa01.marvell.com ([199.233.58.136]) by mx0b-0016f401.pphosted.com with ESMTP id 1f1swt5qtd-6 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=NOT); Mon, 23 Sep 2013 04:11:55 -0700 Received: from maili.marvell.com (10.93.76.43) by sc-owa01.marvell.com (10.93.76.21) with Microsoft SMTP Server id 8.3.213.0; Mon, 23 Sep 2013 04:11:51 -0700 Received: from [10.38.36.114] (unknown [10.38.36.114]) by maili.marvell.com (Postfix) with ESMTP id 016441CCD9C; Mon, 23 Sep 2013 04:11:49 -0700 (PDT) Message-ID: <524021EC.2000207@marvell.com> Date: Mon, 23 Sep 2013 19:11:40 +0800 From: Leo Yan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130804 Thunderbird/17.0.8 MIME-Version: 1.0 To: Lorenzo Pieralisi Subject: Re: [Question] Verification For arm64: suspend/resume implementation References: <52327E41.1070904@marvell.com> <20130913144001.GA28531@e102568-lin.cambridge.arm.com> In-Reply-To: <20130913144001.GA28531@e102568-lin.cambridge.arm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.10.8794, 1.0.431, 0.0.0000 definitions=2013-09-22_03:2013-09-22, 2013-09-22, 1970-01-01 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=7.0.1-1305240000 definitions=main-1309230035 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130923_071225_680367_CC679096 X-CRM114-Status: GOOD ( 42.00 ) X-Spam-Score: -1.9 (-) Cc: Yu Tang , Zhou Zhu , Neil Zhang , "linux-arm-kernel@lists.infradead.org" , "linux-pm@vger.kernel.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 09/13/2013 10:40 PM, Lorenzo Pieralisi wrote: > On Fri, Sep 13, 2013 at 03:53:53AM +0100, Leo Yan wrote: >> hi Lorenzo, >> >> I have applied your ARM64's suspend/resume related patches and can built >> successfully. i want to verify these patches on foundation model >> firstly, so below are my questions: >> >> "Code has been tested on AEM v8 models and a simple CPU idle driver that >> enables a C-state where CPUs are reset when wfi is hit." >> >> 1. Can u help share this simple cpu idle driver? > > Yes, I will post a simple skeleton driver, PSCI based (bootwrapper > implementation), by the end of September. > >> 2. On the foundation model, if the core is placed into reset state, then >> if there have interrupt is routed to the core, the core still cannot be >> waken up anymore; because the reset bit cannot be released by h/w. So >> how can let the core return back from the reset state? > > Well, I am testing it with the AEM models power controller that is not > publicly available yet, and _should_ be released with the new version of the > foundation models. > > As a first step, I will write a PSCI suspend implementation that just executes > wfi and resumes through the reset vector to emulate a power down as a means to > make the suspend/resume code path usable to everyone. > Looking forward the related implementation; After them are ready, i'm glad have a trying. At my side, i'm warming up related doc and tried to debug related tear down opreations according to CA53's TRM; pls see enclosed two patches. Firstly clarify, these two patches are _ONLY_ for debugging purpose, i have no plan to commit them for Linux kernel. 0001-cpuidle-add-simple-driver-for-arm64.patch: it's a simple cpuidle driver; 0002-ARM64-add-cpu-tear-down-function-for-A53-s-power-mod.patch: i tried to wrote a tear down operations (disable D$/flush L1 cache/Disable SMP bit, etc); But i found in the patch 2, if the core execute the instruction "mrs x0, S3_1_C15_C2_1" to access CPUECTLR_EL1, the kernel will report the illegal instructions. So just like before i saw the discussion on mailing list, On ARMv8 we need operate the SMP bit in EL2/EL3/Secure EL1 but not in non-secure EL1. Here i tried two methods to try to fix this issue, but both of them were failure: 1. I tried to set the ACTLR_EL2 bit 1 in the boot wrapper code, but when in the non-secure world's kernel to access CPUECTLR_EL1 it still will report the panic for illegal instruction; 2. I tried to modify the boot wrapper code to let the kernel stay in secure world's EL1, but looks like it also failed; So do u have any suggestion for this failure? Thx, Leo Yan From e238ddfc426bd1f8b2ac3b5f396a31150cbe7e5c Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 23 Sep 2013 17:06:20 +0800 Subject: [PATCH 2/2] ARM64: add cpu tear down function for A53's power mode Signed-off-by: Leo Yan --- arch/arm64/kernel/Makefile | 2 +- arch/arm64/kernel/cpu_tear_down.S | 90 +++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/kernel/cpu_tear_down.S diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 010550a..046fbf0 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,7 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -arm64-obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o +arm64-obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o cpu_tear_down.o arm64-obj-$(CONFIG_SUSPEND) += fake_suspend.o obj-y += $(arm64-obj-y) vdso/ diff --git a/arch/arm64/kernel/cpu_tear_down.S b/arch/arm64/kernel/cpu_tear_down.S new file mode 100644 index 0000000..9f3d5d0 --- /dev/null +++ b/arch/arm64/kernel/cpu_tear_down.S @@ -0,0 +1,90 @@ +/* + * arch/arm64/mach-vexpress/sleep.S + * + * Copyright (c) 2013 Marvell Semiconductor Inc. + * + * Author: Leo Yan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include + +/* + * Exits SMP coherency. + */ +ENTRY(arm64_cpu_tear_down) + mov x12, lr + + mrs x0, sctlr_el1 + bic x0, x0, #1 << 2 // clear SCTLR.C + msr sctlr_el1, x0 + isb + + dsb sy // ensure ordering with previous memory accesses + mrs x0, clidr_el1 // read clidr + and x3, x0, #0x7000000 // extract loc from clidr + lsr x3, x3, #23 // left align loc bit field + cbz x3, finished // if loc is 0, then no need to clean + mov x10, #0 // start clean at cache level 0 + + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask of the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt skip // skip if no cache, or just i-cache + save_and_disable_irqs x9 // make CSSELR and CCSIDR access atomic + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + restore_irqs x9 + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + mov x4, #0x3ff + and x4, x4, x1, lsr #3 // find maximum number on the way size + clz w5, w4 // find bit position of way size increment + mov x7, #0x7fff + and x7, x7, x1, lsr #13 // extract max number of the index size +loop2: + mov x9, x4 // create working copy of max way size +loop3: + lsl x6, x9, x5 + orr x11, x10, x6 // factor way and cache number into x11 + lsl x6, x7, x2 + orr x11, x11, x6 // factor index number into x11 + dc cisw, x11 // clean & invalidate by set/way + subs x9, x9, #1 // decrement the way + b.ge loop3 + subs x7, x7, #1 // decrement the index + b.ge loop2 + +skip: +finished: + mov x10, #0 // swith back to cache level 0 + msr csselr_el1, x10 // select current cache level in csselr + dsb sy + isb + + mrs x0, S3_1_C15_C2_1 + bic x0, x0, #0x1 << 6 // disable SMP bit + msr S3_1_C15_C2_1, x0 + dsb sy + isb + + ret x12 +ENDPROC(arm64_cpu_tear_down) + -- 1.7.9.5