From patchwork Thu Apr 10 13:27:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 3964401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0E41C9F336 for ; Thu, 10 Apr 2014 19:15:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2BD1B20821 for ; Thu, 10 Apr 2014 19:15:30 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C07E120826 for ; Thu, 10 Apr 2014 19:15:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYJrR-0005Hi-DQ; Thu, 10 Apr 2014 18:38:07 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYJqQ-0002PP-Eg; Thu, 10 Apr 2014 18:37:02 +0000 Received: from bombadil.infradead.org ([2001:1868:205::9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYJjo-0001sW-Hx for linux-arm-kernel@merlin.infradead.org; Thu, 10 Apr 2014 18:30:32 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYF10-0000Oy-1R for linux-arm-kernel@lists.infradead.org; Thu, 10 Apr 2014 13:27:38 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3ADR7xm019898; Thu, 10 Apr 2014 08:27:07 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3ADR7CB024105; Thu, 10 Apr 2014 08:27:07 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Thu, 10 Apr 2014 08:27:07 -0500 Received: from [172.24.190.153] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3ADR5nS031943; Thu, 10 Apr 2014 08:27:06 -0500 Message-ID: <53469C29.8050906@ti.com> Date: Thu, 10 Apr 2014 18:57:05 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Russell King - ARM Linux Subject: Re: [PATCH v2 3/3] ARM: OMAP2+: AM43x: L2 cache support References: <20140404101808.GG27282@n2100.arm.linux.org.uk> <53440D73.6060504@ti.com> <20140409162327.GH27282@n2100.arm.linux.org.uk> <534686DF.7070207@ti.com> <20140410120348.GK27282@n2100.arm.linux.org.uk> <53468B8E.9040604@ti.com> In-Reply-To: <53468B8E.9040604@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140410_062738_206259_179BB000 X-CRM114-Status: GOOD ( 15.90 ) X-Spam-Score: -5.6 (-----) Cc: Tony Lindgren , Linux OMAP Mailing List , Linux ARM Mailing List X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thursday 10 April 2014 05:46 PM, Sekhar Nori wrote: > This will work. NS_LOCKDOWN is required for L2C-220 as well and so I was > thinking about adding a new l2c220_enable() which will set the > NS_LOCKDOWN and then call l2c_enable() Here is a patch for what I was saying above. diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index c47ac8f..dc9e03b 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -105,6 +105,8 @@ #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) #define L2X0_AUX_CTRL_ASSOC_SHIFT 13 #define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) +/* L2C-220/310 common bits */ +#define L2C_AUX_CTRL_NS_LOCKDOWN BIT(26) /* L2C-210 specific bits */ #define L210_AUX_CTRL_WRAP_DISABLE BIT(12) #define L210_AUX_CTRL_WA_OVERRIDE BIT(23) @@ -113,7 +115,6 @@ #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) #define L220_AUX_CTRL_FWA_SHIFT 23 #define L220_AUX_CTRL_FWA_MASK (3 << 23) -#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) #define L220_AUX_CTRL_NS_INT_CTRL BIT(27) /* L2C-310 specific bits */ #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ @@ -122,7 +123,6 @@ #define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) #define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ -#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) #define L310_AUX_CTRL_NS_INT_CTRL BIT(27) #define L310_AUX_CTRL_DATA_PREFETCH BIT(28) #define L310_AUX_CTRL_INSTR_PREFETCH BIT(29) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 6b2a056..34cafe0 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -216,8 +216,6 @@ int __init omap4_l2_cache_init(void) { /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ u32 aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR | - L310_AUX_CTRL_NS_LOCKDOWN | - L310_AUX_CTRL_NS_INT_CTRL | L2C_AUX_CTRL_SHARED_OVERRIDE | L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH; diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b1f103d..b6af13f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -498,11 +498,23 @@ static void l2c220_sync(void) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } +static void __init l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) +{ + /* + * Always enable non-secure access to the lockdown registers - + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ + aux |= L2C_AUX_CTRL_NS_LOCKDOWN; + + l2c_enable(base, aux, num_lock); +} + static const struct l2c_init_data l2c220_data = { .type = "L2C-220", .way_size_0 = SZ_8K, .num_lock = 1, - .enable = l2c_enable, + .enable = l2c220_enable, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range, @@ -764,7 +776,7 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); } - l2c_enable(base, aux, num_lock); + l2c220_enable(base, aux, num_lock); if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); @@ -1027,7 +1039,7 @@ static const struct l2c_init_data of_l2c220_data __initconst = { .way_size_0 = SZ_8K, .num_lock = 1, .of_parse = l2x0_of_parse, - .enable = l2c_enable, + .enable = l2c220_enable, .outer_cache = { .inv_range = l2c220_inv_range, .clean_range = l2c220_clean_range,