From patchwork Fri Apr 11 08:49:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 3966831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3964BBFF02 for ; Fri, 11 Apr 2014 08:50:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2DD482080D for ; Fri, 11 Apr 2014 08:50:05 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A7148207F8 for ; Fri, 11 Apr 2014 08:50:03 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WYX9l-0005G1-Up; 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Fri, 11 Apr 2014 09:49:19 +0100 (BST) Received: from [106.116.147.199] by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0N3U007ZWZ660220@eusync3.samsung.com>; Fri, 11 Apr 2014 09:49:18 +0100 (BST) Message-id: <5347AC8A.7090006@samsung.com> Date: Fri, 11 Apr 2014 10:49:14 +0200 From: Tomasz Figa Organization: Samsung R&D Institute Poland User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-version: 1.0 To: Daniel Lezcano , kgene.kim@samsung.com Subject: Re: [PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c References: <1397123751-1957-1-git-send-email-daniel.lezcano@linaro.org> <1397123751-1957-11-git-send-email-daniel.lezcano@linaro.org> <5346A367.2070107@samsung.com> <5346A958.1030302@linaro.org> <5346BA09.9020708@samsung.com> <5347A816.4020609@linaro.org> In-reply-to: <5347A816.4020609@linaro.org> Content-type: multipart/mixed; boundary=------------070903010009080007060308 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjkeLIzCtJLcpLzFFi42I5/e/4Vd3+Ne7BBu+6GS02zljPajHvs6xF 74KrbBbvDz1jttj0+BqrxYzz+5gszpy+xGpx8k8vUNlXDwdOjzvX9rB5bF5S73H732Nmjy1X 21k8+rasYvT4vEkugC2KyyYlNSezLLVI3y6BK+Ph6WPMBffdK94tqmxg/GHVxcjJISFgIjHn wnt2CFtM4sK99WwgtpDAUkaJaatduxi5gOzPjBKNWx6AJXgFtCQaj39lArFZBFQlbm9YCRZn E1CT+NzwCMzmB6pZ03SdBcQWFYiQuNd4mBWiV1Dix+R7YHERAVeJPe8OMYEsYBY4xyix4M9k sKHCAj4SnzZ1sUFsbmOSmDL1DiNIghNo6urFHWA2M1BR+9u3TBMYBWYhGTwLSQrCNpPo2trF CGHLS2x/O4cZwk6R2Nf+gw1TvIFR4tcirwWM7KsYRVNLkwuKk9JzDfWKE3OLS/PS9ZLzczcx QuLryw7GxcesDjEKcDAq8fAeuOQWLMSaWFZcmXuIUQVozqMNqy8wSrHk5eelKonwPlvmHizE m5JYWZValB9fVJqTWnyIkYmDU6qBsbEw3+qF1h4eS71T7UFJbyYuWv1n+aP6+vRTinc1Tdt0 K3UOVdxZvlzTylCXr644cMe5iCM8s7Zu2TH1h5M7u+yK4+XaB2PCTvJxbLi9UPjbzUVbS5hb 2afc2qhl9tdxtSNr3yHnO4b7Is2TFapT3Gd59TxMjmBqMFVTapP84MXacktx5bVCJZbijERD Leai4kQA/RxA+ZkCAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140411_014946_141006_504D3C66 X-CRM114-Status: GOOD ( 25.33 ) X-Spam-Score: -5.6 (-----) Cc: linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, sachin.kamat@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 11.04.2014 10:30, Daniel Lezcano wrote: > On 04/10/2014 05:34 PM, Tomasz Figa wrote: >> On 10.04.2014 16:23, Daniel Lezcano wrote: >>> On 04/10/2014 03:57 PM, Tomasz Figa wrote: >>>> Hi Daniel, >>>> >>>> On 10.04.2014 11:55, Daniel Lezcano wrote: >>>>> One more step is moving the clock ratio setting at idle time in pm.c >>>>> >>>>> The macro names have been changed to be consistent with the other >>>>> macros >>>>> name in the file. >>>>> >>>>> Note, the clock divider was working only when cpuidle was enabled >>>>> because it >>>>> was in its init routine. With this change, the clock divider is set in >>>>> the pm's >>>>> init routine, so it will also operate when the cpuidle driver is not >>>>> set, which >>>>> is good. >>>>> >>>>> Signed-off-by: Daniel Lezcano >>>>> Reviewed-by: Viresh Kumar >>>>> Reviewed-by: Bartlomiej Zolnierkiewicz >>>>> Reviewed-by: Tomasz Figa >>>>> --- >>>>> arch/arm/mach-exynos/cpuidle.c | 54 >>>>> --------------------------------------- >>>>> arch/arm/mach-exynos/pm.c | 35 +++++++++++++++++++++++++ >>>>> arch/arm/mach-exynos/regs-pmu.h | 19 ++++++++++++++ >>>>> 3 files changed, 54 insertions(+), 54 deletions(-) >>>> >>>> Sorry that I didn't mention that before, but now I recall that there >>>> was >>>> already a similar patch moving this code to Exynos5250 clock driver, >>>> which is the best place for setup of any CMU registers and a step >>>> towards removing one more static IO mapping. >>> >>> Yes, Bartlomiej mentioned it. >>> >>> Is it possible to merge this mentioned patch or to give a pointer to it >>> so I can integrate it into the patchset ? >> >> http://marc.info/?l=linux-arm-kernel&m=138147021207626&w=2 >> >> I wonder if it still applies cleanly, though... > > Ok, if I refer to the date, this patch has been lost in the limbus. So I > can integrate it with my patchset without conflicting with any tree. > Right ? > As I suspected, it doesn't apply onto current sources. I have attached a rebased version. Feel free to send it as a part of next version of your series. Best regards, Tomasz From 31d02976c517c1e8d00a0c1296e5fa132af78880 Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Fri, 11 Oct 2013 11:12:14 +0530 Subject: [PATCH] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform. Cc: Abhilash Kesavan Cc: Thomas Abraham Acked-by: Kukjin Kim Reviewed-by: Bartlomiej Zolnierkiewicz Signed-off-by: Amit Daniel Kachhap [t.figa: Rebased onto current kernel sources.] Signed-off-by: Tomasz Figa --- arch/arm/mach-exynos/cpuidle.c | 54 ------------------------------------ drivers/clk/samsung/clk-exynos5250.c | 42 ++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 54 deletions(-) diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index c57cae0..8125a15 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -41,25 +41,6 @@ #define S5P_CHECK_AFTR 0xFCBA0D10 -#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020) -#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024) - -#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) -#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) -#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) -#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) -#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) -#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) -#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) - -#define PWR_CTRL2_DIV2_UP_EN (1 << 25) -#define PWR_CTRL2_DIV1_UP_EN (1 << 24) -#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) -#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) -#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) -#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) - static int exynos4_enter_lowpower(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); @@ -182,46 +163,11 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev, return exynos4_enter_core0_aftr(dev, drv, new_index); } -static void __init exynos5_core_down_clk(void) -{ - unsigned int tmp; - - /* - * Enable arm clock down (in idle) and set arm divider - * ratios in WFI/WFE state. - */ - tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \ - PWR_CTRL1_CORE1_DOWN_RATIO | \ - PWR_CTRL1_DIV2_DOWN_EN | \ - PWR_CTRL1_DIV1_DOWN_EN | \ - PWR_CTRL1_USE_CORE1_WFE | \ - PWR_CTRL1_USE_CORE0_WFE | \ - PWR_CTRL1_USE_CORE1_WFI | \ - PWR_CTRL1_USE_CORE0_WFI; - __raw_writel(tmp, EXYNOS5_PWR_CTRL1); - - /* - * Enable arm clock up (on exiting idle). Set arm divider - * ratios when not in idle along with the standby duration - * ratios. - */ - tmp = PWR_CTRL2_DIV2_UP_EN | \ - PWR_CTRL2_DIV1_UP_EN | \ - PWR_CTRL2_DUR_STANDBY2_VAL | \ - PWR_CTRL2_DUR_STANDBY1_VAL | \ - PWR_CTRL2_CORE2_UP_RATIO | \ - PWR_CTRL2_CORE1_UP_RATIO; - __raw_writel(tmp, EXYNOS5_PWR_CTRL2); -} - static int exynos_cpuidle_probe(struct platform_device *pdev) { int cpu_id, ret; struct cpuidle_device *device; - if (soc_is_exynos5250()) - exynos5_core_down_clk(); - if (soc_is_exynos5440()) exynos4_idle_driver.state_count = 1; diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e7ee442..2bb4625 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -24,6 +24,8 @@ #define APLL_CON0 0x100 #define SRC_CPU 0x200 #define DIV_CPU0 0x500 +#define PWR_CTRL1 0x1020 +#define PWR_CTRL2 0x1024 #define MPLL_LOCK 0x4000 #define MPLL_CON0 0x4100 #define SRC_CORE1 0x4204 @@ -80,6 +82,23 @@ #define SRC_CDREX 0x20200 #define PLL_DIV2_SEL 0x20a24 +/*Below definitions are used for PWR_CTRL settings*/ +#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) +#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) +#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) +#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) +#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) +#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) +#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) +#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) + +#define PWR_CTRL2_DIV2_UP_EN (1 << 25) +#define PWR_CTRL2_DIV1_UP_EN (1 << 24) +#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) +#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) +#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) +#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) + /* list of PLLs to be registered */ enum exynos5250_plls { apll, mpll, cpll, epll, vpll, gpll, bpll, @@ -98,6 +117,8 @@ static struct samsung_clk_reg_dump *exynos5250_save; static unsigned long exynos5250_clk_regs[] __initdata = { SRC_CPU, DIV_CPU0, + PWR_CTRL1, + PWR_CTRL2, SRC_CORE1, SRC_TOP0, SRC_TOP2, @@ -686,6 +707,7 @@ static struct of_device_id ext_clk_match[] __initdata = { /* register exynox5250 clocks */ static void __init exynos5250_clk_init(struct device_node *np) { + unsigned int tmp; if (np) { reg_base = of_iomap(np, 0); if (!reg_base) @@ -722,6 +744,26 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_register_gate(exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); + /* + * Enable arm clock down (in idle) and set arm divider + * ratios in WFI/WFE state. + */ + tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO | + PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | + PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | + PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); + __raw_writel(tmp, reg_base + PWR_CTRL1); + + /* + * Enable arm clock up (on exiting idle). Set arm divider + * ratios when not in idle along with the standby duration + * ratios. + */ + tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN | + PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL | + PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); + __raw_writel(tmp, reg_base + PWR_CTRL2); + exynos5250_clk_sleep_init(); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", -- 1.9.1