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Wed, 07 Jan 2015 18:55:19 +0900 (KST) Message-id: <54AD0293.70909@samsung.com> Date: Wed, 07 Jan 2015 18:55:31 +0900 From: Joonyoung Shim User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-version: 1.0 To: Javier Martinez Canillas , Javier Martinez Canillas , Marek Szyprowski Subject: Re: [PATCH v3 00/19] Exynos SYSMMU (IOMMU) integration with DT and DMA-mapping subsystem References: <1416395748-10731-1-git-send-email-m.szyprowski@samsung.com> <1417514366.21830.22.camel@collabora.co.uk> <54818768.3080303@samsung.com> <54AC93E0.8010705@samsung.com> <54ACFD69.1020500@collabora.co.uk> In-reply-to: <54ACFD69.1020500@collabora.co.uk> X-Brightmail-Tracker: H4sIAAAAAAAAA02SWUxTQRSGnd6tVGuGCjg2LkmN0UAElG0Utycz+qSChuiDlnIDRChNLxB5 UQRUwICUokhxKaYI1IqmqAExbGGLhriERVFQUqMSlNUakEV7qUbfvnPmP//8JzlSSlHOKKXx 2mRer1UnqFgZbfMKFjZfkNyNDHxxLQzPF7Zz2FBlpPDknXMcLnxfQGNzYzhum9Xh3tmrLM4p vc/hPHMPi7syvnI4x2Dh8PfuIQm2O3oZfPV5gwTfbR3g8NO+KRYv5DUD/OtJLYdbh+o5XNzx jcHWx3MAv51djocnOuk9K8nH5hsSYrthA2T2ZyEg85/7aDJfeo4idaYBjpRmlzCkptKX2K05 LKmxnCFvFxwUMb6uAKS7M4MheZmjLMl/YAVkyr72ADwq2xHDJ8Sn8vqAXSdkcdXFM7SuMfhU Rl90OjD55QIPKYLBKMt0E7jZB70YvMfmAplUAcsByq8r5P6Kyp0TtPvhFkC9H4Y4dzEC0M/P 9YyoksNNqNv2kBKZhhtQR+Y4KzIL/dG7Rx0Skb3hEWR44/ij90TTxsFFVy94E6D+63OMWFDQ wSL7q47FUCugBjnNXYsTCmiWoNEiucgeMAB9GTvv+k3qGtiIiooSxTYF16Ea2zdK9EGw2AP1 NEww7kQQ/TC20KIewTXI3kS5V1uFmitf0wXAx/RfJtM/V9N/rmZAWYE3r9PohOhYfZC/oE4U UrSx/pqkRDtwXc+zhU+XasFAU3gLgFKgWibX5dsiFYw6VUhLbAEhrhAGSumtSXIdnDb5+Jag 0K04JDgkaGvYtlDVSnmZciZCAWPVyfxJntfx+uP6lAReaAESqYcyHaSVfLKtr46pzwtZbhmp ONWslB8cmM41Adnq6Jii9nVtw/Jf+SV17RGvRs+WVU5033HsnkvbP+g8PdTp5/QCWVGqqnFN 5JXLhrl9e8f6Dwqx9ytHl9DWsjfaY9ulky97LWPOnfFRwwUjF8jFNYH7n6dEHYpuP9xvzL69 dHWB59fxGRUtxKm3+FJ6Qf0bSeu0IDgDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPKsWRmVeSWpSXmKPExsVy+t9jAd12prUhBre6tC3+TjrGbjFx5WRm i0+rW9ktJt2fwGKxYL+1xdHfBRbXfs9gs+icvYHdonfBVTaLs01v2C06Jy5ht/hy5SGTxabH 11gtZpzfx2Sx9shddotT1z+zWfzrPcho8X/PDnaLIw93s1tMP/6W1WLVrj+MFrd/81m8/HiC xUHc48nBeUwea+atYfT4/WsSo8ff59dZPP7ObmX22DnrLrvH7I6ZrB6bV2h5bFrVyeaxeUm9 x+1/j5k9Jt9Yzuhx5UQTq0dv8zs2j74tqxg9Pm+SCxCIamC0yUhNTEktUkjNS85PycxLt1Xy Do53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAGGhJJCWWJOKVAoILG4WEnfDtOE0BA3XQuY xghd35AguB4jAzSQsIYxY930nywF+00qmq4nNTDO0u5i5OSQEDCRWPr1IwuELSZx4d56ti5G Lg4hgUWMEtcePGSHcF4zSvx6vpsVpIpXQEPiypqtzCA2i4CqxPHmD2wgNpuAnsSdbceZQGxR gTCJiTcfQ9ULSvyYfI8FZJCIwHxGiVtz/7CCOMwCj9kkNl06zghSJSyQLPF1wVmwDiGBBUwS 76bwgticAvoSL963AW3jAGpQl5gyJRckzCwgL7F5zVvmCYwCs5DsmIVQNQtJ1QJG5lWMoqkF yQXFSem5hnrFibnFpXnpesn5uZsYwYntmdQOxpUNFocYBTgYlXh4C/rWhAixJpYVV+YeYpTg YFYS4X3zCyjEm5JYWZValB9fVJqTWnyI0RQYAhOZpUST84FJN68k3tDYxMzI0sjc0MLI2FxJ nFfJvi1ESCA9sSQ1OzW1ILUIpo+Jg1OqgVGk9P5eiaPb19lWxb4Wnbsp7e/qORrG2qFcO8SD 1S+IndvzfH9CqO7KV5Wq7aJiq9ckH00+sUVVtuRJrcfZxprbf542v05uWHQt/8PRjlIOF8OY qsW5FRymn0XXNs3o/9L0VzHigZzgs3U7Yj6+PCz3fMvZQB9vp+zsHUHJtZbOZ5bIT81Zx6zE UpyRaKjFXFScCABqM60OggMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150107_015544_497917_B9ECBDA3 X-CRM114-Status: GOOD ( 26.96 ) X-Spam-Score: -5.0 (-----) Cc: linaro-mm-sig@lists.linaro.org, "linux-samsung-soc@vger.kernel.org" , Shaik Ameer Basha , Arnd Bergmann , Rob Herring , Gustavo Padovan , Joerg Roedel , Will Deacon , iommu@lists.linux-foundation.org, Tomasz Figa , Inki Dae , Sjoerd Simons , Kukjin Kim , Laurent Pinchart , Olof Johansson , Kyungmin Park , Thierry Reding , Cho KyongHo , David Wodhouse , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Javier, On 01/07/2015 06:33 PM, Javier Martinez Canillas wrote: > Hello Joonyoung, > > On 01/07/2015 03:03 AM, Joonyoung Shim wrote: >> On 01/06/2015 06:49 PM, Javier Martinez Canillas wrote: >>> >>> Also I tried forcing the kernel to not disable unused power domains by >>> passing the pd_ignore_unused parameter to the kernel command line. I >>> see on the kernel log a "genpd: Not disabling unused power domains" >>> message but HDMI output still has the stripes that Sjoerd mentioned. >>> Do you know if Exynos DRM HDMI in mainline is supposed to work without >>> SysMMU / IOMMU support? >>> >> >> I don't think iommu support and power domain issue are related. I also >> get displaying stripes via hdmi but it is just power domain issue >> regardless iommu support. >> >> I observed 8th bit from 0x1445000C register of mixer is set to 1 with >> displaying stripes. It means "The graphic layer0 line buffer underflow". >> There was same underflow issue on Exynos4 based boards. As Marek said, >> because LCD0 power domain was turned off. >> > > Interesting, thanks a lot for sharing this information. > >> I just tried to turn off DISP1 power domain at u-boot and DISP1 power >> domain is turned on from kernel hdmi and mixer driver on odroid xu3 >> board. As the result, i can see displaying penguin logo from hdmi. >> > > Can you share the patches you are using to turn on the DISP1 power domain > since AFAIU the kernel does not know about the DISP1 power domain after > commit d51cad7df871 ("ARM: dts: remove display power domain for exynos5420"). > > I tried reverting that commit before so the kernel knows about the DISP1 > power domain and booting with pd_ignore_unused but still had the stripes. > I add DISP1 power domain on dts and please refer below patch[0] with some modification on hdmi phy(Actually, i think this is not related). You also should disable DISP1 power domain from bootloader. >> But the problem exists still because it is failed to control on/off of >> DISP1 power domain more than twice from kernel hdmi and mixer driver.[0] >> > > Something that is not clear to me is how display panel is working on the > Peach boards if this is a power domain issue since according to the manual > both the modules used for display (LCD controller and DP) and the modules > used for HDMI (MIXER and HDMI) belong to the same power domain (DISP1). > I don't know about that because i just tested on odroid xu3 board without display panel. Hmm, It can be any conditions to success on/off power domain e.g. power state of clocks and of on/off order display devices. Is DISP1 power domain disabled on Peach boards to save power, not always on? > Or am I misunderstanding something? > > Thanks a lot for your help and best regards, > Javier > Thanks. [0]: --- arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++ drivers/clk/samsung/clk-exynos5420.c | 4 ++-- drivers/gpu/drm/exynos/exynos_hdmi.c | 8 ++------ include/dt-bindings/clock/exynos5420.h | 2 ++ 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8617a03..ff9ad4a 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -270,6 +270,14 @@ reg = <0x10044120 0x20>; }; + disp1_pd: power-domain@100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>, + <&clock CLK_MOUT_USER_ACLK200_DISP1>; + clock-names = "oscclk", "pclk0", "clk0"; + }; + pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; @@ -704,6 +712,7 @@ "sclk_hdmiphy", "mout_hdmi"; phy = <&hdmiphy>; samsung,syscon-phandle = <&pmu_system_controller>; + samsung,power-domain = <&disp1_pd>; status = "disabled"; }; @@ -717,6 +726,7 @@ interrupts = <0 94 0>; clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "sclk_hdmi"; + samsung,power-domain = <&disp1_pd>; }; gsc_0: video-scaler@13e00000 { diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 848d602..52ba0e6 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -635,7 +635,7 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP3, 0, 1), MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, SRC_TOP3, 4, 1), - MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p, + MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, SRC_TOP3, 12, 1), @@ -693,7 +693,7 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP10, 0, 1), MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, SRC_TOP10, 4, 1), - MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), + MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, SRC_TOP10, 12, 1), MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 563a19e..f3cdf80 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1664,7 +1664,6 @@ static void hdmi_mode_apply(struct hdmi_context *hdata) static void hdmiphy_conf_reset(struct hdmi_context *hdata) { - u8 buffer[2]; u32 reg; clk_disable_unprepare(hdata->res.sclk_hdmi); @@ -1672,11 +1671,8 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) clk_prepare_enable(hdata->res.sclk_hdmi); /* operation mode */ - buffer[0] = 0x1f; - buffer[1] = 0x00; - - if (hdata->hdmiphy_port) - i2c_master_send(hdata->hdmiphy_port, buffer, 2); + hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, + HDMI_PHY_ENABLE_MODE_SET); if (hdata->type == HDMI_TYPE13) reg = HDMI_V13_PHY_RSTOUT; diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 8dc0913..15b9bb2 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -204,6 +204,8 @@ #define CLK_MOUT_MAUDIO0 643 #define CLK_MOUT_USER_ACLK333 644 #define CLK_MOUT_SW_ACLK333 645 +#define CLK_MOUT_USER_ACLK200_DISP1 646 +#define CLK_MOUT_SW_ACLK200 647 /* divider clocks */ #define CLK_DOUT_PIXEL 768