From patchwork Mon Jul 27 07:12:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 6869521 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 725E29F358 for ; Mon, 27 Jul 2015 07:14:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6EDA4205DE for ; Mon, 27 Jul 2015 07:14:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5DEB0205BC for ; Mon, 27 Jul 2015 07:14:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZJcaM-0007id-RV; Mon, 27 Jul 2015 07:12:30 +0000 Received: from mail-wi0-f169.google.com ([209.85.212.169]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZJcaJ-0007Li-4A for linux-arm-kernel@lists.infradead.org; Mon, 27 Jul 2015 07:12:28 +0000 Received: by wibud3 with SMTP id ud3so102008957wib.0 for ; Mon, 27 Jul 2015 00:12:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:reply-to:subject:references:to:cc:from :message-id:date:user-agent:mime-version:in-reply-to:content-type; bh=KEwk8iACQaz3BPYTNUaAiYM3jTbn68oaU64qPvy58Vo=; b=kDHOtbYtiJchfXu4J+6kvIv+Hx8bHlsYAcdthuh6GxZQw0wGtsWyGyrXT5rpD4VQ63 HNiH6m6mMaHPiU6vbzerKhtNx9QQf9Dyu/+sA4wmMW1xcaZHuBG6fgyeM8qJkSBtOGy4 ZZzpH0eVdCEwtqgohYqX62l4NtUWiOwEw/Y6igRuD1ILgNmTTCAWDbfaylrzJ2AWDxGm l+jgJNSuCFpuvPL8CiYs0Cdrtj7r2aEX3PyQvOp7fTqg8c4hwnoKOOe1zx3yEehwe01A DBj2m4KsAzvLbpEIH0Fsf6FMn92IuVXAnRrEKPwD/2jHMAkSTLWFilbYuyNKx4DxDsrf NAXQ== X-Gm-Message-State: ALoCoQmB8QbviKc4i1/dLn5vHftvOzLOTsbp7FqpldErfydIRlSRV9YNFkUhelrCPcY8F4VVDv4k X-Received: by 10.180.182.112 with SMTP id ed16mr20763838wic.19.1437981125075; Mon, 27 Jul 2015 00:12:05 -0700 (PDT) Received: from [192.168.0.102] (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id r19sm11973937wib.7.2015.07.27.00.12.02 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jul 2015 00:12:04 -0700 (PDT) Subject: Re: [RFCv2 3/3] reset: reset-zynq: Adding support for Xilinx Zynq reset controller. References: <1437783682-13632-1-git-send-email-moritz.fischer@ettus.com> <1437783682-13632-4-git-send-email-moritz.fischer@ettus.com> To: Moritz Fischer , p.zabel@pengutronix.de From: Michal Simek X-Enigmail-Draft-Status: N1110 Message-ID: <55B5D9C2.60509@monstr.eu> Date: Mon, 27 Jul 2015 09:12:02 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 MIME-Version: 1.0 In-Reply-To: <1437783682-13632-4-git-send-email-moritz.fischer@ettus.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150727_001227_620673_45C2DCDA X-CRM114-Status: GOOD ( 25.31 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: monstr@monstr.eu Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, soren.brinkmann@xilinx.com, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 07/25/2015 02:21 AM, Moritz Fischer wrote: > This adds a reset controller driver to control the Xilinx Zynq > SoC's various resets. > > Signed-off-by: Moritz Fischer > --- > drivers/reset/Makefile | 1 + > drivers/reset/reset-zynq.c | 142 +++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 143 insertions(+) > create mode 100644 drivers/reset/reset-zynq.c > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 157d421..3fe50e7 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > +obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o > diff --git a/drivers/reset/reset-zynq.c b/drivers/reset/reset-zynq.c > new file mode 100644 > index 0000000..05e37f8 > --- /dev/null > +++ b/drivers/reset/reset-zynq.c > @@ -0,0 +1,142 @@ > +/* > + * Copyright (c) 2015, National Instruments Corp. > + * > + * Xilinx Zynq Reset controller driver > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* Offsets into SLCR regmap */ > +#define SLCR_RST_CTRL_OFFSET 0x200 /* FPGA Software Reset Control */ > + > +#define NBANKS 18 > + > +struct zynq_reset_data { > + struct regmap *slcr; > + struct reset_controller_dev rcdev; > +}; > + > +#define to_zynq_reset_data(p) \ > + container_of((p), struct zynq_reset_data, rcdev) > + > +static int zynq_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); > + > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + Personally me I would also add debug message here to be simply enabled for easier tracking. > + regmap_update_bits(priv->slcr, > + SLCR_RST_CTRL_OFFSET + (bank * 4), > + BIT(offset), > + BIT(offset)); > + > + return 0; > +} > + > +static int zynq_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); > + > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + debug message here too. > + regmap_update_bits(priv->slcr, > + SLCR_RST_CTRL_OFFSET + (bank * 4), > + BIT(offset), > + ~BIT(offset)); > + > + return 0; > +} > + > +static int zynq_reset_status(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev); > + > + int bank = id / BITS_PER_LONG; > + int offset = id % BITS_PER_LONG; > + u32 reg; > + > + regmap_read(priv->slcr, SLCR_RST_CTRL_OFFSET + (bank * 4), ®); debug message here too. > + > + return !(reg & BIT(offset)); > +} > + > +static const struct reset_control_ops zynq_reset_ops = { Remove const here - there is sparse warning. > + .assert = zynq_reset_assert, > + .deassert = zynq_reset_deassert, > + .status = zynq_reset_status, > +}; > + > +static int zynq_reset_probe(struct platform_device *pdev) > +{ > + struct zynq_reset_data *priv; > + > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + platform_set_drvdata(pdev, priv); > + > + priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, > + "syscon"); > + if (IS_ERR(priv->slcr)) { > + dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); > + return PTR_ERR(priv->slcr); > + } > + > + priv->rcdev.owner = THIS_MODULE; > + priv->rcdev.nr_resets = NBANKS * BITS_PER_LONG; > + priv->rcdev.ops = &zynq_reset_ops; > + priv->rcdev.of_node = pdev->dev.of_node; > + reset_controller_register(&priv->rcdev); > + > + return 0; > +} > + > +static int zynq_reset_remove(struct platform_device *pdev) > +{ > + struct zynq_reset_data *priv = platform_get_drvdata(pdev); > + > + reset_controller_unregister(&priv->rcdev); > + > + return 0; > +} > + > +static const struct of_device_id zynq_reset_dt_ids[] = { > + { .compatible = "xlnx,zynq-reset", }, > + { /* sentinel */ }, > +}; > + > +static struct platform_driver zynq_reset_driver = { > + .probe = zynq_reset_probe, > + .remove = zynq_reset_remove, > + .driver = { > + .name = "zynq-pl-reset", > + .of_match_table = zynq_reset_dt_ids, > + }, > +}; > +module_platform_driver(zynq_reset_driver); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Moritz Fischer "); > +MODULE_DESCRIPTION("Zynq Reset Controller Driver"); > Also I am missing enabling reset controller in the arch. Thanks, Michal diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 78e5e007f52d..02a84fdee1bd 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,6 +1,7 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7 select ARCH_SUPPORTS_BIG_ENDIAN + select ARCH_HAS_RESET_CONTROLLER select ARM_AMBA select ARM_GIC select ARM_GLOBAL_TIMER if !CPU_FREQ