From patchwork Fri Nov 20 15:20:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 7669171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 96868BF90C for ; Fri, 20 Nov 2015 15:22:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AE3C12041A for ; Fri, 20 Nov 2015 15:22:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C36DF203F7 for ; Fri, 20 Nov 2015 15:22:43 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZznUb-0004PE-Sq; Fri, 20 Nov 2015 15:20:53 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZznUX-0004AV-B2 for linux-arm-kernel@lists.infradead.org; Fri, 20 Nov 2015 15:20:50 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 20 Nov 2015 07:20:36 -0800 Received: from HQMAIL108.nvidia.com ([172.18.146.13]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 20 Nov 2015 07:08:30 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 20 Nov 2015 07:08:30 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1104.5; Fri, 20 Nov 2015 15:20:27 +0000 Received: from [10.21.132.123] (10.21.132.123) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1104.5; Fri, 20 Nov 2015 15:20:22 +0000 Subject: Re: [PATCH] ARM: tegra: Enable CPUFreq support for Tegra124 Chromebooks To: Tomeu Vizoso , Thierry Reding , References: <1433331821-9648-1-git-send-email-jonathanh@nvidia.com> <556EE8B0.2060205@nvidia.com> <55A3B848.2080205@nvidia.com> <20150915081234.GA25970@ulmo.nvidia.com> <5639F728.6090808@nvidia.com> <5639F7EC.2000508@nvidia.com> <563A06B4.2070005@nvidia.com> From: Jon Hunter Message-ID: <564F3A35.3070708@nvidia.com> Date: Fri, 20 Nov 2015 15:20:21 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <563A06B4.2070005@nvidia.com> X-Originating-IP: [10.21.132.123] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151120_072049_620172_42B89E37 X-CRM114-Status: GOOD ( 21.55 ) X-Spam-Score: -7.5 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "linux-tegra@vger.kernel.org" , Alexandre Courbot , "linux-arm-kernel@lists.infradead.org" , Stephen Warren Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 04/11/15 13:23, Jon Hunter wrote: > > On 04/11/15 12:19, Jon Hunter wrote: >> Correcting Mikko's email ... >> >> On 04/11/15 12:16, Jon Hunter wrote: >>> >>> On 15/09/15 10:00, Tomeu Vizoso wrote: >>>> On 15 September 2015 at 10:12, Thierry Reding wrote: >>>>> On Thu, Sep 03, 2015 at 03:40:45PM +0200, Tomeu Vizoso wrote: >>>>>> On 13 July 2015 at 15:08, Jon Hunter wrote: >>>>>>> On 03/06/15 12:44, Jon Hunter wrote: >>>>>>>> Adding LAKML. Jon >>>>>>>> >>>>>>>> On 03/06/15 12:43, Jon Hunter wrote: >>>>>>>>> Add the device-tree DFLL clock node and CPU regulator phandle for >>>>>>>>> tegra124 chromebooks to enable CPUFreq support on these boards. >>>>>> >>>>>> Ping. >>>>>> >>>>>> Thanks, >>>>> >>>>> Sorry that this has gone unnoticed for so long. I've applied it now to >>>>> the for-4.4/dt branch. >>>>> >>>>> Tomeu, do you want me to add your Tested-by, Reviewed-by or Acked-by >>>>> before I push this out? >>>> >>>> I haven't done proper tests, but I have tested for several weeks a >>>> branch containing these changes on a nyan-big and have found no >>>> issues. >>>> >>>> You can add my Reviewed-by though. Sorry for not having made this clear. >>> >>> I have noticed that system suspend to LP1 is not working on the nyan-big >>> with linux-next and never exits suspend. It appears that this patch is >>> the culprit. I tested cpufreq was changing the frequency as expected but >>> I did not test suspend. > > By the way, LP2 works fine with this change, it is just when LP1 is > enabled (which is the default). Quick update on this ... it appears that the cause of the lock-up is related to pll_x (default pll that clocks the cpu cluster before switching to the dfll). On the jetson-tk1 the pll_x is running at 696MHz where as on the nyan-big it is running at 2.1GHz. Although the pll is disabled when switching to dfll, having it configured for 2.1GHz on the nyan-big is causing a hang during suspend if the dfll is running at much lower frequencies (>1.5GHz) than the pll_x. So seems like the CPU voltage is too low for the pll_x, however, it should be disabled?!? If I hack the cpufreq code to set the pll_x to 696MHz after switching to the dfll on the nyan-big then the problem goes away ... Need to figure out if the suspend code is touching the pll_x. Jon diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 20bcceb58ccc..a87cef4071e8 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -53,6 +53,10 @@ static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv) clk_set_parent(priv->cpu_clk, priv->dfll_clk); + ret = clk_set_rate(priv->pllx_clk, 696000000); + if (ret) + return ret; + return 0;