| Message ID | 584b459ebb0a74a2ce6ca661f1148f59b9014667.1689714291.git.daniel@makrotopia.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC | expand |
On 18/07/2023 23:30, Daniel Golle wrote: > Introduce DT bindings for the MT7988 SoC to mediatek,net.yaml. > The MT7988 SoC got 3 Ethernet MACs operating at a maximum of > 10 Gigabit/sec supported by 2 packet processor engines for > offloading tasks. > The first MAC is hard-wired to a built-in switch which exposes > four 1000Base-T PHYs as user ports. > It also comes with built-in 2500Base-T PHY which can be used > with the 2nd GMAC. > The 2nd and 3rd GMAC can be connected to external PHYs or provide > SFP(+) cages attached via SGMII, 1000Base-X, 2500Base-X, USXGMII, > 5GBase-KR or 10GBase-KR. > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- > .../devicetree/bindings/net/mediatek,net.yaml | 74 +++++++++++++++++-- > 1 file changed, 69 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml > index 38aa3d97ee234..ae2062f3c1833 100644 > --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml > +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml > @@ -24,6 +24,7 @@ properties: > - mediatek,mt7629-eth > - mediatek,mt7981-eth > - mediatek,mt7986-eth > + - mediatek,mt7988-eth > - ralink,rt5350-eth > > reg: > @@ -61,6 +62,12 @@ properties: > Phandle to the mediatek hifsys controller used to provide various clocks > and reset to the system. > > + mediatek,infracfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon node that handles the path from GMAC to > + PHY variants. > + > mediatek,sgmiisys: > $ref: /schemas/types.yaml#/definitions/phandle-array > minItems: 1 > @@ -229,11 +236,7 @@ allOf: > - const: sgmii_ck > - const: eth2pll > > - mediatek,infracfg: > - $ref: /schemas/types.yaml#/definitions/phandle > - description: > - Phandle to the syscon node that handles the path from GMAC to > - PHY variants. > + mediatek,infracfg: true Did it mean that it was defined only here? Then this "true" is not really needed. You should however disallow it ("false") in other variants). Best regards, Krzysztof
On Tue, Jul 18, 2023 at 10:30:33PM +0100, Daniel Golle wrote: > Introduce DT bindings for the MT7988 SoC to mediatek,net.yaml. > The MT7988 SoC got 3 Ethernet MACs operating at a maximum of > 10 Gigabit/sec supported by 2 packet processor engines for > offloading tasks. > The first MAC is hard-wired to a built-in switch which exposes > four 1000Base-T PHYs as user ports. > It also comes with built-in 2500Base-T PHY which can be used > with the 2nd GMAC. > The 2nd and 3rd GMAC can be connected to external PHYs or provide > SFP(+) cages attached via SGMII, 1000Base-X, 2500Base-X, USXGMII, > 5GBase-KR or 10GBase-KR. > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- > .../devicetree/bindings/net/mediatek,net.yaml | 74 +++++++++++++++++-- > 1 file changed, 69 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml > index 38aa3d97ee234..ae2062f3c1833 100644 > --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml > +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml > @@ -24,6 +24,7 @@ properties: > - mediatek,mt7629-eth > - mediatek,mt7981-eth > - mediatek,mt7986-eth > + - mediatek,mt7988-eth > - ralink,rt5350-eth > > reg: > @@ -61,6 +62,12 @@ properties: > Phandle to the mediatek hifsys controller used to provide various clocks > and reset to the system. > > + mediatek,infracfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon node that handles the path from GMAC to > + PHY variants. > + > mediatek,sgmiisys: > $ref: /schemas/types.yaml#/definitions/phandle-array > minItems: 1 > @@ -229,11 +236,7 @@ allOf: > - const: sgmii_ck > - const: eth2pll > > - mediatek,infracfg: > - $ref: /schemas/types.yaml#/definitions/phandle > - description: > - Phandle to the syscon node that handles the path from GMAC to > - PHY variants. > + mediatek,infracfg: true You don't need this. What you need is 'mediatek,infracfg: false' in the if/then schemas for the cases it should not be present. Rob
On Wed, Jul 19, 2023 at 04:13:20PM -0600, Rob Herring wrote: > On Tue, Jul 18, 2023 at 10:30:33PM +0100, Daniel Golle wrote: > > Introduce DT bindings for the MT7988 SoC to mediatek,net.yaml. > > The MT7988 SoC got 3 Ethernet MACs operating at a maximum of > > 10 Gigabit/sec supported by 2 packet processor engines for > > offloading tasks. > > The first MAC is hard-wired to a built-in switch which exposes > > four 1000Base-T PHYs as user ports. > > It also comes with built-in 2500Base-T PHY which can be used > > with the 2nd GMAC. > > The 2nd and 3rd GMAC can be connected to external PHYs or provide > > SFP(+) cages attached via SGMII, 1000Base-X, 2500Base-X, USXGMII, > > 5GBase-KR or 10GBase-KR. > > > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > > --- > > .../devicetree/bindings/net/mediatek,net.yaml | 74 +++++++++++++++++-- > > 1 file changed, 69 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml > > index 38aa3d97ee234..ae2062f3c1833 100644 > > --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml > > +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml > > @@ -24,6 +24,7 @@ properties: > > - mediatek,mt7629-eth > > - mediatek,mt7981-eth > > - mediatek,mt7986-eth > > + - mediatek,mt7988-eth > > - ralink,rt5350-eth > > > > reg: > > @@ -61,6 +62,12 @@ properties: > > Phandle to the mediatek hifsys controller used to provide various clocks > > and reset to the system. > > > > + mediatek,infracfg: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to the syscon node that handles the path from GMAC to > > + PHY variants. > > + > > mediatek,sgmiisys: > > $ref: /schemas/types.yaml#/definitions/phandle-array > > minItems: 1 > > @@ -229,11 +236,7 @@ allOf: > > - const: sgmii_ck > > - const: eth2pll > > > > - mediatek,infracfg: > > - $ref: /schemas/types.yaml#/definitions/phandle > > - description: > > - Phandle to the syscon node that handles the path from GMAC to > > - PHY variants. > > + mediatek,infracfg: true > > You don't need this. What you need is 'mediatek,infracfg: false' in the > if/then schemas for the cases it should not be present. > Ack, will do in the next round. Thanks!
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index 38aa3d97ee234..ae2062f3c1833 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt7629-eth - mediatek,mt7981-eth - mediatek,mt7986-eth + - mediatek,mt7988-eth - ralink,rt5350-eth reg: @@ -61,6 +62,12 @@ properties: Phandle to the mediatek hifsys controller used to provide various clocks and reset to the system. + mediatek,infracfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon node that handles the path from GMAC to + PHY variants. + mediatek,sgmiisys: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 @@ -229,11 +236,7 @@ allOf: - const: sgmii_ck - const: eth2pll - mediatek,infracfg: - $ref: /schemas/types.yaml#/definitions/phandle - description: - Phandle to the syscon node that handles the path from GMAC to - PHY variants. + mediatek,infracfg: true mediatek,sgmiisys: minItems: 2 @@ -315,6 +318,67 @@ allOf: minItems: 2 maxItems: 2 + - if: + properties: + compatible: + contains: + const: mediatek,mt7988-eth + then: + properties: + interrupts: + minItems: 4 + + clocks: + minItems: 34 + maxItems: 34 + + clock-names: + items: + - const: crypto + - const: fe + - const: gp2 + - const: gp1 + - const: gp3 + - const: ethwarp_wocpu2 + - const: ethwarp_wocpu1 + - const: ethwarp_wocpu0 + - const: esw + - const: netsys0 + - const: netsys1 + - const: sgmii_tx250m + - const: sgmii_rx250m + - const: sgmii2_tx250m + - const: sgmii2_rx250m + - const: top_usxgmii0_sel + - const: top_usxgmii1_sel + - const: top_sgm0_sel + - const: top_sgm1_sel + - const: top_xfi_phy0_xtal_sel + - const: top_xfi_phy1_xtal_sel + - const: top_eth_gmii_sel + - const: top_eth_refck_50m_sel + - const: top_eth_sys_200m_sel + - const: top_eth_sys_sel + - const: top_eth_xgmii_sel + - const: top_eth_mii_sel + - const: top_netsys_sel + - const: top_netsys_500m_sel + - const: top_netsys_pao_2x_sel + - const: top_netsys_sync_250m_sel + - const: top_netsys_ppefb_250m_sel + - const: top_netsys_warp_sel + - const: wocpu1 + - const: wocpu0 + - const: xgp1 + - const: xgp2 + - const: xgp3 + + mediatek,sgmiisys: + minItems: 2 + maxItems: 2 + + mediatek,infracfg: true + patternProperties: "^mac@[0-1]$": type: object
Introduce DT bindings for the MT7988 SoC to mediatek,net.yaml. The MT7988 SoC got 3 Ethernet MACs operating at a maximum of 10 Gigabit/sec supported by 2 packet processor engines for offloading tasks. The first MAC is hard-wired to a built-in switch which exposes four 1000Base-T PHYs as user ports. It also comes with built-in 2500Base-T PHY which can be used with the 2nd GMAC. The 2nd and 3rd GMAC can be connected to external PHYs or provide SFP(+) cages attached via SGMII, 1000Base-X, 2500Base-X, USXGMII, 5GBase-KR or 10GBase-KR. Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- .../devicetree/bindings/net/mediatek,net.yaml | 74 +++++++++++++++++-- 1 file changed, 69 insertions(+), 5 deletions(-)