| Message ID | 59a0d43f34b69406cd320f16edc4e7fabe022bfd.1611756920.git.baruch@tkos.co.il (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | phy: qualcomm: support IPQ60xx USB PHY | expand |
Hi Kathiravan T, Thanks for your review. On Fri, Feb 05 2021, Kathiravan T wrote: > On 2021-01-27 19:50, Baruch Siach wrote: >> From: Kathiravan T <kathirav@codeaurora.org> >> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> >> [baruch: adjust regs address/size; drop binding updates; >> drop unsupported quirk properties] >> Signed-off-by: Baruch Siach <baruch@tkos.co.il> >> --- >> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 ++++ >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++++++++++++++++++ >> 2 files changed, 56 insertions(+) >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> index 99cefe88f6f2..5aec18308712 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> @@ -78,3 +78,11 @@ nand@0 { >> nand-bus-width = <8>; >> }; >> }; >> + >> +&qusb_phy_1 { >> + status = "ok"; >> +}; >> + >> +&usb2 { >> + status = "ok"; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> index 9fa5b028e4f3..d4a3d4e4a7e9 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> @@ -524,6 +524,54 @@ qrtr_requests { >> }; >> }; >> + qusb_phy_1: qusb@59000 { >> + compatible = "qcom,ipq6018-qusb2-phy"; >> + reg = <0x0 0x059000 0x0 0x180>; >> + #phy-cells = <0>; >> + >> + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, >> + <&xo>; >> + clock-names = "cfg_ahb", "ref"; > > As per the bindings, ref clock should be 19.2MHz where the XO in IPQ60xx is > 24MHz. Did the USB enumerated successfully and able to perform read / write > operations? I managed to enumerate an Ethernet USB dongle with only this series applied. But then I tested again with USB storage device. That only worked with downstream clock adjust/period patch: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/commit/?h=fig&id=707d8fa2b481888f4792edc6561e81999301cbcf That patch applies cleanly on top of v5.11-rc4. Is anyone at Codeaurora pushing the dwc3 clock patch upstream? Should I do that? Thanks, baruch
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 99cefe88f6f2..5aec18308712 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -78,3 +78,11 @@ nand@0 { nand-bus-width = <8>; }; }; + +&qusb_phy_1 { + status = "ok"; +}; + +&usb2 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9fa5b028e4f3..d4a3d4e4a7e9 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -524,6 +524,54 @@ qrtr_requests { }; }; + qusb_phy_1: qusb@59000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x059000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; + status = "disabled"; + }; + + usb2: usb2@7000000 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x070F8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names = "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <24000000>; + resets = <&gcc GCC_USB1_BCR>; + status = "disabled"; + + dwc_1: dwc3@7000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x7000000 0x0 0xcd00>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_1>; + phy-names = "usb2-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + }; wcss: wcss-smp2p {