| Message ID | 5a6fc55341b346439ba32b5a3e14087edbaa6226.1598621459.git.cristian.ciocaltea@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add initial support for RoseapplePi SBC | expand |
On 0828, Cristian Ciocaltea wrote: > Add a Device Tree for the RoseapplePi SBC. > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > Reviewed-by: Peter Korsgaard <peter@korsgaard.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 ++++++++++++++++++++++ > 2 files changed, 48 insertions(+) > create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 4572db3fa5ae..bff9ef996fbb 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ > dtb-$(CONFIG_ARCH_ACTIONS) += \ > owl-s500-cubieboard6.dtb \ > owl-s500-guitar-bb-rev-b.dtb \ > + owl-s500-roseapplepi.dtb \ > owl-s500-sparky.dtb > dtb-$(CONFIG_ARCH_PRIMA2) += \ > prima2-evb.dtb > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts > new file mode 100644 > index 000000000000..a2087e617cb2 > --- /dev/null > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Roseapple Pi > + * > + * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > + */ > + > +/dts-v1/; > + > +#include "owl-s500.dtsi" > + > +/ { > + compatible = "roseapplepi,roseapplepi", "actions,s500"; > + model = "Roseapple Pi"; > + > + aliases { > + serial2 = &uart2; > + }; > + > + chosen { > + stdout-path = "serial2:115200n8"; > + }; > + > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x80000000>; /* 2GB */ > + }; > + > + uart2_clk: uart2-clk { > + compatible = "fixed-clock"; > + clock-frequency = <921600>; > + #clock-cells = <0>; > + }; > +}; > + > +&twd_timer { > + status = "okay"; > +}; > + > +&timer { > + clocks = <&hosc>; > +}; > + > +&uart2 { > + status = "okay"; > + clocks = <&uart2_clk>; > +}; > -- > 2.28.0 >
On Mon, Aug 31, 2020 at 02:56:48PM +0530, Manivannan Sadhasivam wrote: > On 0828, Cristian Ciocaltea wrote: > > Add a Device Tree for the RoseapplePi SBC. > > > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > > Reviewed-by: Peter Korsgaard <peter@korsgaard.com> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Cristi > Thanks, > Mani > > > --- > > arch/arm/boot/dts/Makefile | 1 + > > arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 ++++++++++++++++++++++ > > 2 files changed, 48 insertions(+) > > create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts > > > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > > index 4572db3fa5ae..bff9ef996fbb 100644 > > --- a/arch/arm/boot/dts/Makefile > > +++ b/arch/arm/boot/dts/Makefile > > @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ > > dtb-$(CONFIG_ARCH_ACTIONS) += \ > > owl-s500-cubieboard6.dtb \ > > owl-s500-guitar-bb-rev-b.dtb \ > > + owl-s500-roseapplepi.dtb \ > > owl-s500-sparky.dtb > > dtb-$(CONFIG_ARCH_PRIMA2) += \ > > prima2-evb.dtb > > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts > > new file mode 100644 > > index 000000000000..a2087e617cb2 > > --- /dev/null > > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts > > @@ -0,0 +1,47 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Roseapple Pi > > + * > > + * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > > + */ > > + > > +/dts-v1/; > > + > > +#include "owl-s500.dtsi" > > + > > +/ { > > + compatible = "roseapplepi,roseapplepi", "actions,s500"; > > + model = "Roseapple Pi"; > > + > > + aliases { > > + serial2 = &uart2; > > + }; > > + > > + chosen { > > + stdout-path = "serial2:115200n8"; > > + }; > > + > > + memory@0 { > > + device_type = "memory"; > > + reg = <0x0 0x80000000>; /* 2GB */ > > + }; > > + > > + uart2_clk: uart2-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <921600>; > > + #clock-cells = <0>; > > + }; > > +}; > > + > > +&twd_timer { > > + status = "okay"; > > +}; > > + > > +&timer { > > + clocks = <&hosc>; > > +}; > > + > > +&uart2 { > > + status = "okay"; > > + clocks = <&uart2_clk>; > > +}; > > -- > > 2.28.0 > >
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..bff9ef996fbb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_ACTIONS) += \ owl-s500-cubieboard6.dtb \ owl-s500-guitar-bb-rev-b.dtb \ + owl-s500-roseapplepi.dtb \ owl-s500-sparky.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts new file mode 100644 index 000000000000..a2087e617cb2 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Roseapple Pi + * + * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "roseapplepi,roseapplepi", "actions,s500"; + model = "Roseapple Pi"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; + + uart2_clk: uart2-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&twd_timer { + status = "okay"; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart2_clk>; +};