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[178.255.168.35]) by mx.google.com with ESMTPSA id t9sm11879583wjf.41.2014.10.20.06.25.47 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 20 Oct 2014 06:25:47 -0700 (PDT) From: Michal Simek To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/3] ARM: zynq: Extend SLCR driver to read OCM configuration Date: Mon, 20 Oct 2014 15:25:33 +0200 Message-Id: <5d26a2b4b91eb33e42491b65f893c97c6ffd6ee5.1413811526.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <742a19eb987f3f99b42ba4b7e7ebc27bf19d7d72.1413811526.git.michal.simek@xilinx.com> References: <742a19eb987f3f99b42ba4b7e7ebc27bf19d7d72.1413811526.git.michal.simek@xilinx.com> In-Reply-To: <742a19eb987f3f99b42ba4b7e7ebc27bf19d7d72.1413811526.git.michal.simek@xilinx.com> References: <742a19eb987f3f99b42ba4b7e7ebc27bf19d7d72.1413811526.git.michal.simek@xilinx.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141020_062614_778024_E48B619D X-CRM114-Status: GOOD ( 14.12 ) X-Spam-Score: 1.3 (+) Cc: Josh Cartwright , monstr@monstr.eu, Russell King , Daniel Lezcano , Peter Crosthwaite , linux-kernel@vger.kernel.org, Steffen Trumtrar , Soren Brinkmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, T_TVD_MIME_NO_HEADERS, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get OCM configuration from SLCR. Signed-off-by: Michal Simek --- Changes in v2: None arch/arm/mach-zynq/slcr.c | 15 +++++++++++++++ include/soc/zynq/common.h | 1 + 2 files changed, 16 insertions(+) -- 1.8.2.3 diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 22d9d54d2333..3f65e2027875 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -27,6 +27,7 @@ #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */ +#define SLCR_OCM_CFG_OFFSET 0x910 /* OCM Address Mapping */ #define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_A9_CPU_CLKSTOP 0x10 @@ -126,6 +127,20 @@ void zynq_slcr_system_reset(void) } /** + * zynq_slcr_get_ocm_config - Get SLCR OCM config + * + * Return: OCM config bits + */ +u32 zynq_slcr_get_ocm_config(void) +{ + u32 val; + + zynq_slcr_read(&val, SLCR_OCM_CFG_OFFSET); + + return val; +} + +/** * zynq_slcr_cpu_start - Start cpu * @cpu: cpu number */ diff --git a/include/soc/zynq/common.h b/include/soc/zynq/common.h index 2bc71273c73c..3d0b9a6d76ab 100644 --- a/include/soc/zynq/common.h +++ b/include/soc/zynq/common.h @@ -27,6 +27,7 @@ extern void zynq_slcr_cpu_start(int cpu); extern bool zynq_slcr_cpu_state_read(int cpu); extern void zynq_slcr_cpu_state_write(int cpu, bool die); extern u32 zynq_slcr_get_device_id(void); +extern u32 zynq_slcr_get_ocm_config(void); #ifdef CONFIG_SMP extern void secondary_startup(void);