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Thu, 28 Mar 2024 23:15:17 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 28 Mar 2024 23:15:16 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v4 4/6] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_issue_cmdlist() Date: Thu, 28 Mar 2024 23:14:08 -0700 Message-ID: <5f1283471b5e0fe415afc7af3b6db7d06f21ff53.1711690673.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|BL1PR12MB5945:EE_ X-MS-Office365-Filtering-Correlation-Id: 620fdab4-09e7-47bf-2bc7-08dc4fb7a2ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aJIQQY59UzjpSt2z3+GRQqc1qgnt9a/hMUOc0WzRWp69MPiruTF/6tP3qT39DMPLKWoOaPMFQ5zYjUHXA/5qA83wqEaVIOAp4+7EN3i53VOsms5fbpOtsyU39ONsXRF7F5SREcyuOz0LJQ5Rf067MWpKAzLBB6j88rnofBRcZpgQuNBbx3bDNClTn9TtYritjjrgoNmoB3ijVP5DPs40TPhID8EFHLxs17ebozzQbMvRw/5qXouw1pvZZLXDan6pAnV6iWRe43rr1z98fs+UGL8755nEGyakDV/+xXSTr6wK7M90YYwtE5nh2kFAKkHj1XDOHGnWME3sTwlAtzTW+oADczD6w0XSn8Ure+icShupBysqw/1qpA8wmA55mD8wjvK2n3VedDVHybMt9q2m+BAKLGA76oLd0tR7G/emPTkuvrNByeQ2/92rgxHV7/0VNBvy6uewfMw6yt48YQaSu0AaSWRdVDmKtb0ZkqyqLzYT3PqxKhOZ1KSf+lca/Mm3fH2YfOnulgr2FR35Kr8yBP4YOLIEhiu6zE1k7YDQhJcPFz/C2yBlNG41Wqlu8zL9th5b2tjTwnZIaJQIv+as64LUxMX6T1X7M/X4IvCMYHh5Cu6AnZT8SbGNbd0SZVWPPMg6s0sNJPZjdx7Abd1hgLFB7JMXFkhsiLEbhGmbOQVzP8BktWvJ6G2XLmwkdfNyXS6b8NaK1i4TY3fqeUsFxbfIBo4slnPqEhexJyzJ/qgj0Hg/Ql/rg3hGH/BHD6Wa X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2024 06:15:30.5455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 620fdab4-09e7-47bf-2bc7-08dc4fb7a2ba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5945 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240328_231536_758756_4D16AF1D X-CRM114-Status: GOOD ( 12.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The driver currently calls arm_smmu_get_cmdq() helper in different places, although they are all called from the arm_smmu_cmdq_issue_cmdlist(). Allow to pass in the cmdq pointer, instead of calling arm_smmu_get_cmdq() every time. This will also help CMDQV extension in NVIDIA Tegra241 SoC, as its driver will maintain its own cmdq pointers, then need to redirect arm_smmu->cmdq to one of its vcmdqs upon seeing a supported command. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6cb20bff5a8a..7630c1dd5235 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -603,11 +603,11 @@ static void arm_smmu_cmdq_poll_valid_map(struct arm_smmu_cmdq *cmdq, /* Wait for the command queue to become non-full */ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { unsigned long flags; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); int ret = 0; /* @@ -638,11 +638,11 @@ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { int ret = 0; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); queue_poll_init(smmu, &qp); @@ -662,10 +662,10 @@ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 prod = llq->prod; int ret = 0; @@ -712,13 +712,14 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, } static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { if (smmu->options & ARM_SMMU_OPT_MSIPOLL && !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) - return __arm_smmu_cmdq_poll_until_msi(smmu, llq); + return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); - return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); + return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); } static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds, @@ -775,7 +776,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, while (!queue_has_space(&llq, n + sync)) { local_irq_restore(flags); - if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) + if (arm_smmu_cmdq_poll_until_not_full(smmu, cmdq, &llq)) dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); local_irq_save(flags); } @@ -851,7 +852,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, /* 5. If we are inserting a CMD_SYNC, we must wait for it to complete */ if (sync) { llq.prod = queue_inc_prod_n(&llq, n); - ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); + ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq); if (ret) { dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout at 0x%08x [hwprod 0x%08x, hwcons 0x%08x]\n",