From patchwork Tue Oct 6 08:23:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Fedin X-Patchwork-Id: 7333681 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F1D119F1D5 for ; Tue, 6 Oct 2015 08:26:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 00248205C2 for ; Tue, 6 Oct 2015 08:26:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 238BF204FB for ; Tue, 6 Oct 2015 08:26:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZjNY7-0004yx-QE; Tue, 06 Oct 2015 08:24:39 +0000 Received: from mailout2.w1.samsung.com ([210.118.77.12]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZjNXw-0004ln-RJ for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2015 08:24:30 +0000 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NVS00LF8I04IC80@mailout2.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2015 09:24:04 +0100 (BST) X-AuditID: cbfec7f5-f794b6d000001495-53-561385245f31 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 4C.A8.05269.42583165; Tue, 6 Oct 2015 09:24:04 +0100 (BST) Received: from fedinw7x64.rnd.samsung.ru ([106.109.131.169]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NVS00KBMI00MUA0@eusync4.samsung.com>; Tue, 06 Oct 2015 09:24:04 +0100 (BST) From: Pavel Fedin To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] exynos_mct: Allow to use architected timer mode Date: Tue, 06 Oct 2015 11:23:59 +0300 Message-id: <64e124ca664a6eb266af33cc178fa4749a0c1358.1444119342.git.p.fedin@samsung.com> X-Mailer: git-send-email 2.4.4 In-reply-to: References: In-reply-to: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmluLIzCtJLcpLzFFi42I5/e/4NV2VVuEwg+aHIhb9j18zW2x6fI3V 4vZlXgdmj5bmHjaPTas62Tw2L6kPYI7isklJzcksSy3St0vgymi47VLwU6ji+4boBsb7/F2M nBwSAiYSxw81M0HYYhIX7q1n62Lk4hASWMoo8efAEWYIp41J4uf7CSwgVWwC6hKnv34As0UE NCSmdD1mB7GZBTwkHh17wwpiCwu4SFz4uAZsKouAqkT36Y/MIDavQLRE6/urUNvkJK5cn84G YnMKmEvcv3kbLC4kYCbx9+onVlziExj5FzAyrGIUTS1NLihOSs810itOzC0uzUvXS87P3cQI CaKvOxiXHrM6xCjAwajEwytxUyhMiDWxrLgy9xCjBAezkgjvTy7hMCHelMTKqtSi/Pii0pzU 4kOM0hwsSuK8M3e9DxESSE8sSc1OTS1ILYLJMnFwSjUwOp/4/URYartlduEkNh42UendO07l fIk9sdA5q+1n72zniXY/b3/RfxklnPXEa+EXg10aXm+/CgsFdrhvclEP3Z3G6Zt09gjfnVP7 I78+uxTA//J5auetx55l2zpihd5K3jrxVW3pwS1n3FfNn8FZVqNnapOpaz7hwrLWrFedbFIr bnwKnKxhrcRSnJFoqMVcVJwIAL7URW8eAgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151006_012429_235121_32477E4F X-CRM114-Status: GOOD ( 19.78 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kukjin Kim , Russell King MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MCT is actually compatible with architected timer and can be accessed using CP15 registers. This allows to use virtualization extensions on Exynos boards, provided you have the appropriate bootloader. Compatibility mode is enabled if armv7-timer device node is inserted into MCT node. In this case the driver will only enable counter and exit, leaving the rest for the architected timer driver. Signed-off-by: Pavel Fedin --- drivers/clocksource/exynos_mct.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 029f96a..a48492d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -510,7 +510,7 @@ static struct notifier_block exynos4_mct_cpu_nb = { .notifier_call = exynos4_mct_cpu_notify, }; -static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base) +static void __init exynos4_timer_resources(struct device_node *np) { int err, cpu; struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); @@ -527,10 +527,6 @@ static void __init exynos4_timer_resources(struct device_node *np, void __iomem panic("%s: unable to retrieve mct clock instance\n", __func__); clk_prepare_enable(mct_clk); - reg_base = base; - if (!reg_base) - panic("%s: unable to ioremap mct address space\n", __func__); - if (mct_int_type == MCT_INT_PPI) { err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], @@ -574,8 +570,19 @@ out_irq: static void __init mct_init_dt(struct device_node *np, unsigned int int_type) { + struct device_node *child; u32 nr_irqs, i; + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: unable to ioremap mct address space\n", __func__); + + for_each_child_of_node(np, child) + if (of_device_is_compatible(child, "arm,armv7-timer")) { + exynos4_mct_frc_start(); + return; + } + mct_int_type = int_type; /* This driver uses only one global timer interrupt */ @@ -594,7 +601,7 @@ static void __init mct_init_dt(struct device_node *np, unsigned int int_type) for (i = MCT_L0_IRQ; i < nr_irqs; i++) mct_irqs[i] = irq_of_parse_and_map(np, i); - exynos4_timer_resources(np, of_iomap(np, 0)); + exynos4_timer_resources(np); exynos4_clocksource_init(); exynos4_clockevent_init(); }