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[68.185.59.186]) by smtp.gmail.com with ESMTPSA id e11sm14280165pgp.10.2016.12.16.15.18.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Dec 2016 15:18:06 -0800 (PST) From: Joshua Clayton To: Alan Tull , Moritz Fischer , Russell King , Catalin Marinas , Will Deacon , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [PATCH v6 2/5] lib: implement __arch_bitrev8x4() Date: Fri, 16 Dec 2016 15:17:51 -0800 Message-Id: <6c1c052d3c1d0c02a791aaaf8e114360ab1cb4e7.1481918884.git.stillcompiling@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161216_151829_898259_6A3B0C10 X-CRM114-Status: GOOD ( 10.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Joshua Clayton , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Anatolij Gustschin , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement faster bitrev8x4() for arm, arm64 and mips, all the platforms with CONFIG_HAVE_ARCH_BITREVERSE. ARM platforms just need a byteswap added to the existing __arch_bitrev32() Amusingly, the mips implementation is exactly the opposite, requiring removal of the byteswap from its __arch_bitrev32() Signed-off-by: Joshua Clayton --- arch/arm/include/asm/bitrev.h | 6 ++++++ arch/arm64/include/asm/bitrev.h | 6 ++++++ arch/mips/include/asm/bitrev.h | 6 ++++++ include/linux/bitrev.h | 1 + 4 files changed, 19 insertions(+) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h index ec291c3..9482f78 100644 --- a/arch/arm/include/asm/bitrev.h +++ b/arch/arm/include/asm/bitrev.h @@ -17,4 +17,10 @@ static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) return __arch_bitrev32((u32)x) >> 24; } +static __always_inline __attribute_const__ u32 __arch_bitrev8x4(u32 x) +{ + __asm__ ("rbit %0, %1; rev %0, %0" : "=r" (x) : "r" (x)); + return x; +} + #endif diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h index a5a0c36..1801078 100644 --- a/arch/arm64/include/asm/bitrev.h +++ b/arch/arm64/include/asm/bitrev.h @@ -16,4 +16,10 @@ static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) return __arch_bitrev32((u32)x) >> 24; } +static __always_inline __attribute_const__ u32 __arch_bitrev8x4(u32 x) +{ + __asm__ ("rbit %0, %1; rev %0, %0" : "=r" (x) : "r" (x)); + return x; +} + #endif diff --git a/arch/mips/include/asm/bitrev.h b/arch/mips/include/asm/bitrev.h index bc739a4..9ac6439 100644 --- a/arch/mips/include/asm/bitrev.h +++ b/arch/mips/include/asm/bitrev.h @@ -27,4 +27,10 @@ static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) return ret; } +static __always_inline __attribute_const__ u32 __arch_bitrev8x4(u32 x) +{ + u32 ret; + asm("bitswap %0, %1" : "=r"(ret) : "r"(x)); + return ret; +} #endif /* __MIPS_ASM_BITREV_H__ */ diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 868dcb6..b1cfa1a 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -9,6 +9,7 @@ #define __bitrev32 __arch_bitrev32 #define __bitrev16 __arch_bitrev16 #define __bitrev8 __arch_bitrev8 +#define __bitrev8x4 __arch_bitrev8x4 #else extern u8 const byte_rev_table[256];