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Thu, 28 Mar 2024 23:15:13 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v4 1/6] iommu/arm-smmu-v3: Add CS_NONE quirk Date: Thu, 28 Mar 2024 23:14:05 -0700 Message-ID: <6e1704f99d8f31b7abe653fe95f459377857937b.1711690673.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4F:EE_|MN2PR12MB4343:EE_ X-MS-Office365-Filtering-Correlation-Id: caefcdb2-6aa3-43a4-d929-08dc4fb79f80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AUkP+oRyt0zynWwQ6GRHj+Q6/y0cV+qT0I0RnaJKu+hiPl9TDeTdmi20FpUb/hU/u+Szb+nREKZ1xco7NA0QlUKK8O6HoN7xTX6778o+ViecUPAfD6akxugGk85+XAJEjtPneJEbjuCnbyDPSnoFwvWUP/qfEXeyV25suyEH8kL+2muNjrqenpFHYoNq3olLIVqfHrMlxX0tCDnmH61v610er253pW7rbFHy+ABvsU5069qW9NbtV7gEVy9b8EE3lIqLLQPlhuOZYL/Gbpf9ySHIPC7OMPYkIMRA1CuIgKMs08lndvTQ+idn25MOZA1mvez3nBaJ7krN5IiMaMoous/HpUqEOwHMdAxHn7JVFz2rOV1ISXmSKbn7lw0In+M7Y9SkOdLvquW8/edfZKUxUn1RizqY0OC/if/YOMzluRxJmYap3G/EAgCEpRWqzO2kTajA15EOhfQBHQowPeHxPXKiCMZ9dZXKJif4pDsnrxhQnUFOdH+YKlrHptUekQd4fHajXvAsHJ0E1AsVYj0oNTrAxjXqqJpeZkV/gSmwEsIxVGI0Z/wC58+sV/bxHzSIGpnxjMFAiGRTJoRzLQY+QPlOWdunBOynFw4tRHPpuNqd4nMFy7ajjRCyp2uMx4pkXYBVOpaLrXZQI/6sofhgYhzmoZXcJpXKobUuHbwaBJ4qegf6UQvu1gi3+2GsnahvTatWCWqtMmyTUHc9HdcanHok/YiOumC6e2L8lhcjvFddPgAi8w3qjdFuN4zQJ0m8 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2024 06:15:25.2148 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: caefcdb2-6aa3-43a4-d929-08dc4fb79f80 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4343 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240328_231538_385338_18A4647C X-CRM114-Status: GOOD ( 14.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a quirk flag to accommodate that. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 5ed036225e69..da3957ad95be 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -334,7 +334,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { + if (ent->sync.cs_none) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + } else if (ent->sync.msiaddr) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; } else { @@ -371,6 +373,9 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, q->ent_dwords * 8; } + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) + ent.sync.cs_none = true; + arm_smmu_cmdq_build_cmd(cmd, &ent); } @@ -707,7 +712,8 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) return __arm_smmu_cmdq_poll_until_msi(smmu, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 23baf117e7e4..b95d9a9ae0a8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -509,6 +509,7 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_CMD_SYNC 0x46 struct { u64 msiaddr; + bool cs_none; } sync; }; }; @@ -541,6 +542,9 @@ struct arm_smmu_queue { u32 __iomem *prod_reg; u32 __iomem *cons_reg; + +#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */ + u32 quirks; }; struct arm_smmu_queue_poll {