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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xjdgMKkeBH0+Fv6PYUNsOWoUFAgNbH6/PB8YdwR+I1bq194UWZmprCddt87D+4zKVnpjJrUwESgwv7SVCcEI3vccjTu7LSp/3Cq99t5vLCiaeKhunej/oS0Xw/ZvMoKdv74nU80UUQZSFBab1MJC/zEB1gjeyYUBLD4uNmLeGVZ3mxScxZq5xS7cYMznzWwGKoF0TwY7KcWUJkkowpD9mtL1jkvtKdZgH6A139PN7XSJYgEczrqsgfok5Yj0uFfdVhcsP1KV6pW0Sp1VKgvyT6dB8+RPp//qLCjf9Vyt1dUXZgzQXoHLhb7KmA5dNHIMYeYNVMP8cYpHUyppBbTugNHBeke4pEbD9h95IWfhZvue11eXOj5KYSeRukIwRdxIs3fYkyXO3oyMjSMQX9+FRYPEHUWaOBAyxaIrSjl8oQ6OY9S2895p+jy5WzRCyDpH7guVrDI36QZ4PKgLGkVG9+3k11ahc7xb6d56LWmHFd+vbMXl4gBCwlnEFQSbAOiNrLeOqEbS/zuOcqq6Qk8LTscYB4Sch+QbGRovd7GwRZ5bJ9ajiP6nrKEYGK4TjLiKksZ40HHpJcQySQcmeJz+mV35IkNDvPShZtSFxNaA2hLKN+B1MqM+aPeHEwM4fVeywaI9EoFbYx7L/dE2WfDFsA8rPaZ0qj4p8ygMUYEx5WYHgjy4eBl/ijV3lOFXJgdy456oFhaUR5TJoPrd0SfUHAdCDTsOKi2ROFOaaIlu0G/9UhJZJE2ltTqRxLPZwNSaNd8T6Q/QnHzE/drEHMUeKqCiIiTgKDmf5qYfq0/OgyUVHT1rh73NkbsQ4LTRRgtETANqUgXU06UyrlLFskzUjBftDEEGMTgtzMVI3B0rK+xbsSSb24zUBy2tiC9LfRBUUIYiMKY8NEZ0thV7CZZ15ghz3zVweDZgJS091ym+Ikkxw9sOWXSyZmj+naNwjx/rOQoWQ6g2nOP487CC7TVDiSsNAGgDiRTbXuOaHkEt7kHnQXsWcxnKH7MRa7bdn3M41FZekRmlyrXEQRHmX4bXJZ+w0sB7sLMI5MfTJnDwdY+UsA6TzA745zwlfhQs8tAQ1+AhPnkdxjdEqqV++umyLZpxMwQ7aDa7noVgqMxc+NJhMq4Ci398kwzFcp5lHzP8ZAU2RpXwRjmYCd+TikIET28rnDsOOom2gQgS0K35pAvNyTCg82OjFNeueq4JK+7cEhBxGInQEkoyj/jClCcHwz+zTueRHtBJ9dvtfzngyY4s4aNUctztjCbxDwGEUyHWUwJgk2s75m+8DB/n51p+kkv2aPQo8UoTUQgRohGRR/Y0bd3qIr0/z2JxTwhtqABjKVUr5N6bda9h5TKIUMTR3KmAQGhEJdcXs7JfR2z2wo7wdb8McRUsR8ipn1zBmrGB+nPypYNVPAIsvao0btmGN04TvpUzd+vzu9s34FHUfHoszKbO7aqVvA0UYTsWYLADr7PMe27SlNp1ZrcpL4bFO60Ma5Pnh4L208bbWoWB7U9jmA2RXGxBcjDFZOEgZOv+FrtFJYCBiqDT56sb30Xl5WY6znqFTiCqZoXAZ+KxoRvqI3/EHjg+gLkbD2y2/hrO X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ed40ebd5-1381-4c06-0bc6-08dbdb336978 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2023 23:36:46.3655 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ayRNVu2u4gVQbIYYzw7d7/PqTyZ2ZDYMbfKk1Witk/FNr/cgHiwbgImXlgufFlQp X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5301 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_163724_257384_AECDF480 X-CRM114-Status: GOOD ( 19.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce arm_smmu_make_s1_cd() to build the CD from the paging S1 domain, and reorganize all the places programming S1 domain CD table entries to call it. Split arm_smmu_update_s1_domain_cd_entry() from arm_smmu_update_ctx_desc_devices() so that the S1 path has its own call chain separate from the unrelated SVA path. arm_smmu_update_s1_domain_cd_entry() only works on S1 domains attached to RIDs and refreshes all their CDs. Remove the forced clear of the CD during S1 domain attach, arm_smmu_write_cd_entry() will do this automatically if necessary. Signed-off-by: Jason Gunthorpe --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 25 +++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 60 +++++++++++++------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 +++ 3 files changed, 75 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 521bfa18879f90..04a807774402b2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -54,6 +54,29 @@ static void arm_smmu_update_ctx_desc_devices(struct arm_smmu_domain *smmu_domain spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); } +static void +arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_master *master; + struct arm_smmu_cd target_cd; + unsigned long flags; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + struct arm_smmu_cd *cdptr; + + /* S1 domains only support RID attachment right now */ + cdptr = arm_smmu_get_cd_ptr(master, IOMMU_NO_PASID); + if (WARN_ON(!cdptr)) + continue; + + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + arm_smmu_write_cd_entry(master, IOMMU_NO_PASID, cdptr, + &target_cd); + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); +} + /* * Check if the CPU ASID is available on the SMMU side. If a private context * descriptor is using it, try to replace it. @@ -97,7 +120,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) * be some overlap between use of both ASIDs, until we invalidate the * TLB. */ - arm_smmu_update_ctx_desc_devices(smmu_domain, IOMMU_NO_PASID, cd); + arm_smmu_update_s1_domain_cd_entry(smmu_domain); /* Invalidate TLB entries previously associated with that context */ arm_smmu_tlb_inv_asid(smmu, asid); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 790e7911714dc8..46d0a45fb0f525 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1118,8 +1118,8 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, WRITE_ONCE(*dst, cpu_to_le64(val)); } -static struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, - u32 ssid) +struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, + u32 ssid) { __le64 *l1ptr; unsigned int idx; @@ -1181,9 +1181,9 @@ static bool arm_smmu_write_cd_step(struct arm_smmu_cd *cur, } -static void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, - struct arm_smmu_cd *cdptr, - const struct arm_smmu_cd *target) +void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, + struct arm_smmu_cd *cdptr, + const struct arm_smmu_cd *target) { struct arm_smmu_cd target_used; @@ -1195,6 +1195,32 @@ static void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, } } +void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, + struct arm_smmu_master *master, + struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; + + memset(target, 0, sizeof(*target)); + + target->data[0] = cpu_to_le64( + cd->tcr | +#ifdef __BIG_ENDIAN + CTXDESC_CD_0_ENDI | +#endif + CTXDESC_CD_0_V | + CTXDESC_CD_0_AA64 | + (master->stall_enabled ? CTXDESC_CD_0_S : 0) | + CTXDESC_CD_0_R | + CTXDESC_CD_0_A | + CTXDESC_CD_0_ASET | + FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) + ); + + target->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); + target->data[3] = cpu_to_le64(cd->mair); +} + void arm_smmu_clear_cd(struct arm_smmu_master *master, int ssid) { struct arm_smmu_cd target = {}; @@ -2609,29 +2635,29 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); switch (smmu_domain->stage) { - case ARM_SMMU_DOMAIN_S1: + case ARM_SMMU_DOMAIN_S1: { + struct arm_smmu_cd target_cd; + struct arm_smmu_cd *cdptr; + if (!master->cd_table.cdtab) { ret = arm_smmu_alloc_cd_tables(master); if (ret) goto out_list_del; - } else { - /* - * arm_smmu_write_ctx_desc() relies on the entry being - * invalid to work, clear any existing entry. - */ - ret = arm_smmu_write_ctx_desc(master, IOMMU_NO_PASID, - NULL); - if (ret) - goto out_list_del; } - ret = arm_smmu_write_ctx_desc(master, IOMMU_NO_PASID, &smmu_domain->cd); - if (ret) + cdptr = arm_smmu_get_cd_ptr(master, IOMMU_NO_PASID); + if (!cdptr) { + ret = -ENOMEM; goto out_list_del; + } + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + arm_smmu_write_cd_entry(master, IOMMU_NO_PASID, cdptr, + &target_cd); arm_smmu_make_cdtable_ste(&target, master, &master->cd_table); arm_smmu_install_ste_for_dev(master, &target); break; + } case ARM_SMMU_DOMAIN_S2: arm_smmu_make_s2_domain_ste(&target, master, smmu_domain); arm_smmu_install_ste_for_dev(master, &target); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index a8e7574ab8e154..950f5a08acda6d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -764,6 +764,14 @@ extern struct mutex arm_smmu_asid_lock; extern struct arm_smmu_ctx_desc quiet_cd; void arm_smmu_clear_cd(struct arm_smmu_master *master, int ssid); +struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, + u32 ssid); +void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, + struct arm_smmu_master *master, + struct arm_smmu_domain *smmu_domain); +void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, + struct arm_smmu_cd *cdptr, + const struct arm_smmu_cd *target); int arm_smmu_write_ctx_desc(struct arm_smmu_master *smmu_master, int ssid, struct arm_smmu_ctx_desc *cd);