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Tue, 6 Aug 2024 19:12:03 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 6/9] iommu/arm-smmu-v3: Add ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY Date: Tue, 6 Aug 2024 19:11:51 -0700 Message-ID: <716ac3e9d2564bbc47390160286a9ce1a1d85704.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|LV3PR12MB9235:EE_ X-MS-Office365-Filtering-Correlation-Id: c2e8a8bb-ec72-4e7e-7617-08dcb6865f84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: JHlJxQqZbGr4uVaLs4EdWIbR9nc6/T0XQI46J9VvbumSqo98xDKCNileH/pTPay/2LP3kOeWvHlUm0Xri+o5DskWhJDTOwv0JKiNFUV7/zltHfF0a0192I8nK1XPUhpTHzYT0v/cZr1txHNuKdMrlcquJJ7/ua6jav5BKqHjI90eZafKZuLmXZb9hIbxFfSlV6rho3PyAyjYTA0wyUI6lN/qEckGhecGYhSBK2c3la9deqM1rYRZ7//fSjLokLPFbC4l9AmAhETlx18++6O4Pdss4RQtige/Hm6B16nySSxgBP7v2Eb6YBZzlTexnFDJo/lNnRMBNHgW4p3q8kfv1f5xwxiSjOWOtpEVKl3ffXwQwba+xL9+J1theTh3GFK0ozTg/VxvSkI8X5Xz5xuNo2tsf8tRxCkOo6dQw/pRqjapxgmtnFUEVPWJ/Aqqdpy1XhhLCoiLmRaFUCy1mpsyS0ktGBxtouvEcS1BB371EpqcUFj7k2+xkzr3Q3jM8v1fQwJWuoUUcsoy8sSORXcmW4CjXGWaSa8eBrLZklu1grso+RFyD6VnXkVnChSS6BGMbgBLbv9lr5oBlakbgseSvKphPoTLx3BTsbJk6oPJ8hdNHiXWw2kS/vLelV6EDyqReYC3XUc3ojOjpXoZSrldCNNsCva9KQ/n+aQzeimmsHvjyeGyHD41+7MmZDL3zby79gS8ktieFLV0Ud7kDHASgaKJ2NhlgbvNYuAOlagt5Bu0YVeE84U8400Jwb2QGo1WdGO+9CXQTl1HIKKk7HSc5u2Q/tflECj6ABQ1OpxWVY+6KjG0vmGoDTXbzMyJhAf+KsCb+nnFXRtqwrVvIyACKQnu+r36VgUUObti5qtyKiCKq5SRnuAi1vBuNJzEUpFKsALN59UYtAjrpb55lz2e0l3Ru3KcEdncLwqRmRvsi8ItGmHlf5FeYZQn/E+3pejJw5U5RUF3ouAX0jnEXgSBOadsOCeNQTGq3iP+9PccUqegJ7Oyf7FvntQT8WEstj8boTVVq64Zpt3ippNVuqslSMzUlvGdG3V6JjWpiQvsvZiBK26at41nUndMYlPunBaFtiKqlmJr8dq25uq/81BDSAibN27WtUhGC9W0CVgiyKk2192I/fp+tl5z3vdsW1+0sPFRSxUJwHckwehfXSnasnmTBbSpirkr4OzFcAnJVVOJNcYGYPH5eJehZqPy5/GMffoJMXNkQu96fn7XnSOee++aOMYKQLLQuBAOBMhr6wmgtfe8FBVq8/UvvZ04iEmW9WGvm+Jqp+QfJgRw/SNEFFaK83fOdl2UhB5h8095PL4RftzrcrTdGafROaPbjarm/snIkEpre3BDGrduCC+sa2nFAOb8lLXbCgZ/2VhmE2HFbNiF78tOodFoQWNpXjr98p5LCwBWKqh37+iEa5zDG13CFkOVUZcroiQcmIYc5YZTA6iA/Kv+1+LllNsjv+VC X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:22.2750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2e8a8bb-ec72-4e7e-7617-08dcb6865f84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9235 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240806_191229_767488_E2D59B7C X-CRM114-Status: GOOD ( 12.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a new SMMU option to accommodate that. Suggested-by: Will Deacon Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 ++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 +++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index df1149095860..e764236a9216 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -341,6 +341,15 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) return &smmu->cmdq; } +static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) +{ + if (cmdq == &smmu->cmdq) + return false; + + return smmu->options & ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY; +} + static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, u32 prod) { @@ -351,6 +360,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + return; + } + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); return; @@ -697,7 +711,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6c5dc2f10a33..71818f586036 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -658,10 +658,11 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_HD (1 << 22) u32 features; -#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) -#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) -#define ARM_SMMU_OPT_MSIPOLL (1 << 2) -#define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) +#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_MSIPOLL (1 << 2) +#define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) +#define ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY (1 << 4) u32 options; struct arm_smmu_cmdq cmdq;