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Thu, 29 Aug 2024 15:34:44 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v14 02/10] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_build_sync_cmd Date: Thu, 29 Aug 2024 15:34:31 -0700 Message-ID: <723288287997b6dfbcd2a904d2c11e9b23f82250.1724970714.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000009:EE_|SJ0PR12MB6855:EE_ X-MS-Office365-Filtering-Correlation-Id: 08c2b92b-2979-4e1a-98bc-08dcc87acfd3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: movTb436d7+mTRd6erde10Ob0fE9VjFFRA3kX2uZc7WnZNSaN+kNcpWqzpB1C2oGgy9FKYj/F3vE6zlzTYfegI8ieG1Vv3wLjCYrH1fKpEjOoGszT2A8oLBH6Cw92/p/lwvHRcV1iHf2VvJyyjlb0pxL4JdsvwL47zI8hiYR/bGMn/CcoshRBcgQ2vfSLizZCPnf8pBGG+rwP6ya2tOgwcfNAj7yJpngfMfY+77Xfe7t8LIK1MsaE37bKQQXNusAoFelc7GaQeMdtuuHpMHmJzIMLpSRzWaZqiDUpPHN6Nr+kAfJSEkrRxeyEAXO7LzSuwUsz6vJQtvcC8kWEzFU/MKvd4q8keoW7FGeXDLYXwzBcqeGgLV4yPRubElnL10iZWVuXa+VlH6kP8DGWBnmtS6ouTYccIcz6PHXZL/SL5pON1sazl40gBEAs1QAENuexrbjI+cxLZn45SSNs7ArK5IeUAU9dxUC2+0gjuUX5nSLdqcHJPpiUpkeo4A60t92WDEzF544g3mwt9WVx44YJqgA1Ng4/b9fS8T+v7SYsMt2jbhDlydfRYX+TfNoud4eQWd2rlxRPLRS7kYLFcmoJYAt1EjUtBUI5RB7U/4yWiunXejv7+yvgIqvEp530YSoKKouhsvxTN9B6MCYvYukQOgJ8yY7Y/u7p/O5mxqGcAkPdsXM7QuDMLbpWEzc3XnEz0zFu6vl9WR7UfIRYjtPWbTVR8JHzH34Z2MHkP5p8Ey8QNO7LAwvDCNXV6pZba6XwtfUtYV5JDSed21awjsr497Hc8K38li4gD3yWVlE3yMDpil5TjScp0599QahTa5YIeY074JZjLzmInuCAYLvs4eWBMgE7BnR+DKS8XSZml8f2Zfugjtq6fsXtWK9NZ0dVLPR6W8UxY0+UQsRMX3mqd3Z+sk8Bp6ij4RKmNUe8MCbRD+w5BN/t0xAfAOVkqmP7Rol7yIXRskDG8EgKV9njJcho0eark3+yM+PPsomNa4YnpC7ols/Bv4GVi12T4l94qHzFi7jA1dLFzIHL8FqxUlTmn7jtGYz0BEgK8NtgJ3wKSveDs3KvSQCMGhcNth3fGuACnQ+P+k2ZL6nReAiil++M3AEXPW+2Hjn9GT9b3lU6Dl2PEpCYMB3EsTvZWDeFhMF0ybYccMln18Gg/MQiyIfZV9AWawGumnK+pYiwNOL/Mkc48gUa6/m90VhXlJ457PArAIYGGfz6bhzs8z4QRFs++GeDFOajKZFMnVf+lgp3/P5arDSb/4lz+E9tc82a+EFefmInD5QhBiYDFEG5ibBOAyz6Nkrq4TeGp9YNFb8BPdoh8Pkl7smUsNPgT5Npe908JYthtu6EatoDZlO/2vQKKQZ/Fw09GLK7z7uzI3voo/uMAYSveJJNLI11/FCDHtRdz82wQLmRbWO7yru/GYWvo5sgpC3d9fOOKAPg2TfHLS+RnYMo+nhP/ZZxibP X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 22:34:57.6521 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08c2b92b-2979-4e1a-98bc-08dcc87acfd3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6855 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240829_153509_327807_3AA8CEB1 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension on NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC, v.s. standard SMMU CMDQ. Pass in the cmdq pointer directly, so the function can identify a different cmdq implementation. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 7213ec538887..4a28cd2dc47a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -352,8 +352,9 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) } static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, - struct arm_smmu_queue *q, u32 prod) + struct arm_smmu_cmdq *cmdq, u32 prod) { + struct arm_smmu_queue *q = &cmdq->q; struct arm_smmu_cmdq_ent ent = { .opcode = CMDQ_OP_CMD_SYNC, }; @@ -371,7 +372,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, } static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) + struct arm_smmu_cmdq *cmdq) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -379,6 +380,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", [CMDQ_ERR_CERROR_ATC_INV_IDX] = "ATC invalidate timeout", }; + struct arm_smmu_queue *q = &cmdq->q; int i; u64 cmd[CMDQ_ENT_DWORDS]; @@ -427,7 +429,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); + __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); } /* @@ -790,7 +792,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n); if (sync) { prod = queue_inc_prod_n(&llq, n); - arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); + arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod); queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); /*