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Thu, 15 Aug 2024 17:55:43 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v12 06/10] iommu/arm-smmu-v3: Add ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY Date: Thu, 15 Aug 2024 17:55:27 -0700 Message-ID: <727ac09c5f660b113b95fe9951b77b2755ce33d9.1723754745.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E62:EE_|DS0PR12MB8342:EE_ X-MS-Office365-Filtering-Correlation-Id: 95c4292f-20e8-4f9d-62b0-08dcbd8e335f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: wnfj6ZzILzS4ZDwNH8kFzy+gn1i0kcBjnxxuI3QjRaKwGrZPvHl++/zi1gD2oVt48Omzw2BHqcvRxX5atgwFwUSc1SZVxE5spCeh5lCCubT4QJmLczZPDqfcPbeHi/aeoF+W/QGR0L27MKhOGIrIhx81GPmSe8vHT2nyikRQJDctK0Eha4i97xTGyYTm2zmjdtxKE6l9gaGCOWpK0ZEtfoB/3tZxs6zY+V6ZG+41UfOrH2KIjueWUS+sX2+8DRv0xw8xIRIAhil4DvP/IALPuxSIQYJhxeI1LGyBPE/wCtMhnxzdYP9jQ6XmUIjyKp6iSW6YHtfIAE4WO7WgR94jKa1W9SMZx80weOFu4qA2+jjR6HYNsyEoahy6Uwt6rkm2FB70TrtJ22PeEtPhvU+vCdEJYkdGmTAh+q1t5m3AIyy8eGZWq8wq4mhHfgyE9vejfbo3ESCsIvGHiTDe70RG1ObakI08/WfiTD6ZU+URnYkzpsJaL4cmtZ3TN6qNlNlfiKiA5tQbpG0eKyQXS+L3vXztgTCbA4ngu/HRgPtW/h3saULg8OEHwn8xedk0atLZL9Wf4F8S0re1el7ibEv2QKqXcvqWNSmiSdY3F3ZsG3O56W/JqViiAlIOn5PvHMrKS3oT3MZ32hMSR5RWhkaPtPHRsb6Xxhpn9goKosJLCB0eZZ7BnUhrsZvc9SrnIJn7R2bR6KYCMGK1lYip8VSAg2wHz2wCfNkPekfCmW4+ZRSCsD4jl77RyolJ/cgr3vpLRZ/O1rkxL4MSTJGWFMvqx+M/1DZoZpeM/kB/z2FFW/SKPyJar7VllXUEhYo1EAnzF06aoyKncNOLORMTNBAOSzux8YMxTebOEELjxsHpctpCK+GzrAuLouFcyFiK+oE3GFyB2dhTm535yfx9+r4RFLe37HYDbtxd1AxhbTjWAYebG/YWdM5t/ERW46esTgzie5d/p8cKKRD49fhD55RMY00O8B9wVQB1JKRmP1i5z8FDb9GastendZhxEGbbk+wTIW6e6xtT+9FjguiSxzC6gE6wgGQS+ZyNe2CayVaV3zOuVwQHm29sa8G5yqr1nqZodLd4uqZJkuOhGIuP+lDi1Iw8BiAIo6NyKJ3o+J0Rg2rBgj9KW5+ZtYHljx0hWWHU6P6sF5fqitKFCggX320g0l0r5lNha2wA42Y2Iv5LewVoWgPsbmZPNvXFFNPr15x8zUNT46u1qYnjaSJ1cdj31Mpq86+R5yBpsi1Sczc0v1knbptPxD6FbqRSs/uPi/gGqFyNZzCePaeD30mOfxXmM+CWwF+sAGhvZObWUadU8GRJMyIGGvBu5kMJsvdknhrbsOx0KM0nsdIPffK4CAwjR61N8HGSxRz0nlE/QIL89AXccHPromo+xab4kQIjfwGME+qzRqrCk+KvVu30ALK6WZKshCLTSUaeRQVWjmJeoLbHLQxGYUCpN1Qw1O3gpo6p X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 00:56:02.2631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95c4292f-20e8-4f9d-62b0-08dcbd8e335f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8342 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_175610_848596_32746D18 X-CRM114-Status: GOOD ( 12.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a new SMMU option to accommodate that. Suggested-by: Will Deacon Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 ++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 +++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index df1149095860..e764236a9216 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -341,6 +341,15 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) return &smmu->cmdq; } +static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) +{ + if (cmdq == &smmu->cmdq) + return false; + + return smmu->options & ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY; +} + static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, u32 prod) { @@ -351,6 +360,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + return; + } + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); return; @@ -697,7 +711,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6c5dc2f10a33..71818f586036 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -658,10 +658,11 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_HD (1 << 22) u32 features; -#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) -#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) -#define ARM_SMMU_OPT_MSIPOLL (1 << 2) -#define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) +#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_MSIPOLL (1 << 2) +#define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) +#define ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY (1 << 4) u32 options; struct arm_smmu_cmdq cmdq;