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Tue, 6 Aug 2024 19:12:00 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 3/9] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_build_sync_cmd Date: Tue, 6 Aug 2024 19:11:48 -0700 Message-ID: <728977eae3b97466c4afe89111ab0543b0eeb59b.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB71:EE_|BL1PR12MB5825:EE_ X-MS-Office365-Filtering-Correlation-Id: 75286605-6d1f-4c68-128f-08dcb6865d0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: fH/ZpPUvlUzZdzZpZGNNTT0ATGOZp7RL2R2/7OWxONQ7D4K3b35eCRn+N9TPHMou/2ZBGGTbTPnQR2R/xRgQduV73M5Jh4vF0uHtImAOhoVc3ltPU+3n5kjtP4F4GFyP9PdZDrDL8E/iSuhv+i68B5sJXLiMXDRL0Y3hru5iKL5nsQS5oRlX+rLLDYGPRhoxQi8kTRobRWqPPONWonMZwF2MvW3r3LrgeCQhyQRlklkfVb2hGwR+21W/YmP80pibN6kd482rhFBi1R3AXWs8DylkUmurFkqKQ/ILNaxlPAKy22XV8kXprp42VGXHo/wZXgDebHGTiK08BgguEI210VboVcVtli61r/3VlAlHq1Pytxnv0jEWtF0LIJjwKyOHmLfd2On0qKOMN/lzZUed5qYSXo+Bk7KGYOgN4ffs5eYTgWE18jn9Dn3rIhfVz+tcPUHbFZXWkTLntc0js7gKUFezULd1dJJvsSXLU4sdgOEILTvr9TK3B2CtmsFsh9xZ8WUXIe5jrpIChiHfTCeeT3590dUIHA46sCaEDiV1FhqJDSs8jhq5mjZTa/VGnStguMaMm8BdbGtMBZLgq+GE2dohYS/ed3PBKHUDiPGROrCHYAP2+fQvYT2scJrRnoN6nMda5L8BxEcXJ11CMzv4P236REUzNpDeT7/eAN2RbOn2Ezyy6DjBYcGTCh8JwH4lnWAPNL7QghqdwFggj5wjHSVth48vJNOfYTBBmabKpZf+KM6KPoqs3AuYkraTpQDb27X1tsjvQ1DoGghzS+Ik7I5uvov2YaHRVMDB4zW36YIPPe0UTwrPJLabgZJV2Rt+qRRt1T5ogNG08xJB64u2QRsPRT0gIjDqtkRGVldB6+ja+9SupYu5oIj9ypsOiODQtEesVI+JbdHCqKvxJOTCfYwkSxxDasGXvfxedJJsoNPb5Ns1ZLcJuaZA5RaIIk8W2PelK+Z1Rn283ME1lgBHH4R3nl1ARBymMDNHQxh+2nNXdvp5wvj35EcVSOTSJHfTyJtVH72HpLt0ksIUcXrEfFgGRB+CdFtGQw7QrowUbV0AzvdORqii6cqvBCcg77ewEPQnQWuCPqersnhYcUf9DHrp6ZTdfiqnMPHFV+v2WMWcWSl3iYdtUtiZ49d+1ZB49ZVRRyvA2q49oNtjidfdZB7ntDqG+/1fdl3Wb6rB7eAKDxtgycoAsu2/eTPO0p1bSomd6S2w9c60/g2l46XS9SAhA1UMplz/qMQ+pC1AyN4GUS4379GBlXuqfMtOzX8HJ8STQcNKhOs5p7ouKCslqx1Z7bng0Q7NTt0YPkjq9h4W3XhGr2dTznMPmLKgnfcCXNQEM6k+O17pBtmiblWXmZBGLbBU8HCvVSYOx8dTA0TIZlpKIbkE/fY7w2gthLOs5sujUE7dV7Axm3wekxarWquyCI5FJBFdZmp5pz09iUvFOvsMo2Ev91PYLgAZSw/9 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:18.0969 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75286605-6d1f-4c68-128f-08dcb6865d0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB71.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5825 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240806_191227_395220_3D7C14F2 X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension on NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC, v.s. standard SMMU CMDQ. Pass in the cmdq pointer directly, so the function can identify a different cmdq implementation. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f481d7be3d4e..d11362e9fc8a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -342,8 +342,10 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) } static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, - struct arm_smmu_queue *q, u32 prod) + struct arm_smmu_cmdq *cmdq, u32 prod) { + struct arm_smmu_queue *q = &cmdq->q; + cmd[1] = 0; cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | @@ -364,7 +366,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, } static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) + struct arm_smmu_cmdq *cmdq) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -372,6 +374,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", [CMDQ_ERR_CERROR_ATC_INV_IDX] = "ATC invalidate timeout", }; + struct arm_smmu_queue *q = &cmdq->q; int i; u64 cmd[CMDQ_ENT_DWORDS]; @@ -410,14 +413,14 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, cmdq, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); + __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); } /* @@ -780,7 +783,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n); if (sync) { prod = queue_inc_prod_n(&llq, n); - arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); + arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod); queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); /*