diff mbox series

[v3,30/39] arm64: kasan: Enable TBI EL1

Message ID 733e94d7368b54473b242bb6a38e421cf459c9ad.1600987622.git.andreyknvl@google.com
State New, archived
Headers show
Series kasan: add hardware tag-based mode for arm64 | expand

Commit Message

Andrey Konovalov Sept. 24, 2020, 10:50 p.m. UTC
From: Vincenzo Frascino <vincenzo.frascino@arm.com>

Hardware tag-based KASAN relies on Memory Tagging Extension (MTE) that is
built on top of the Top Byte Ignore (TBI) feature.

Enable in-kernel TBI when CONFIG_KASAN_HW_TAGS is turned on by enabling
the TCR_TBI1 bit in proc.S.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Co-developed-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Andrey Konovalov <andreyknvl@google.com>
---
Change-Id: I91944903bc9c9c9044f0d50e74bcd6b9971d21ff
---
 arch/arm64/mm/proc.S | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

Comments

Catalin Marinas Sept. 25, 2020, 11:37 a.m. UTC | #1
On Fri, Sep 25, 2020 at 12:50:37AM +0200, Andrey Konovalov wrote:
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 12ba98bc3b3f..dce06e553c7c 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -40,9 +40,13 @@
>  #define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
>  
>  #ifdef CONFIG_KASAN_SW_TAGS
> -#define TCR_KASAN_FLAGS TCR_TBI1
> +#define TCR_KASAN_SW_FLAGS TCR_TBI1
>  #else
> -#define TCR_KASAN_FLAGS 0
> +#define TCR_KASAN_SW_FLAGS 0
> +#endif
> +
> +#ifdef CONFIG_KASAN_HW_TAGS
> +#define TCR_KASAN_HW_FLAGS TCR_TBI1
>  #endif
>  
>  /*
> @@ -454,6 +458,9 @@ SYM_FUNC_START(__cpu_setup)
>  
>  	/* set the TCR_EL1 bits */
>  	orr	mte_tcr, mte_tcr, #SYS_TCR_EL1_TCMA1
> +#ifdef CONFIG_KASAN_HW_TAGS
> +	orr	mte_tcr, mte_tcr, #TCR_KASAN_HW_FLAGS
> +#endif

I missed this in an earlier patch. Do we need TCMA1 set without
KASAN_HW? If not, we could add them both to TCR_KASAN_HW_FLAGS.
Vincenzo Frascino Sept. 25, 2020, 11:47 a.m. UTC | #2
On 9/25/20 12:37 PM, Catalin Marinas wrote:
> On Fri, Sep 25, 2020 at 12:50:37AM +0200, Andrey Konovalov wrote:
>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
>> index 12ba98bc3b3f..dce06e553c7c 100644
>> --- a/arch/arm64/mm/proc.S
>> +++ b/arch/arm64/mm/proc.S
>> @@ -40,9 +40,13 @@
>>  #define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
>>  
>>  #ifdef CONFIG_KASAN_SW_TAGS
>> -#define TCR_KASAN_FLAGS TCR_TBI1
>> +#define TCR_KASAN_SW_FLAGS TCR_TBI1
>>  #else
>> -#define TCR_KASAN_FLAGS 0
>> +#define TCR_KASAN_SW_FLAGS 0
>> +#endif
>> +
>> +#ifdef CONFIG_KASAN_HW_TAGS
>> +#define TCR_KASAN_HW_FLAGS TCR_TBI1
>>  #endif
>>  
>>  /*
>> @@ -454,6 +458,9 @@ SYM_FUNC_START(__cpu_setup)
>>  
>>  	/* set the TCR_EL1 bits */
>>  	orr	mte_tcr, mte_tcr, #SYS_TCR_EL1_TCMA1
>> +#ifdef CONFIG_KASAN_HW_TAGS
>> +	orr	mte_tcr, mte_tcr, #TCR_KASAN_HW_FLAGS
>> +#endif
> 
> I missed this in an earlier patch. Do we need TCMA1 set without
> KASAN_HW? If not, we could add them both to TCR_KASAN_HW_FLAGS.
> 

We don't. I will move the code around in the next version.
diff mbox series

Patch

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 12ba98bc3b3f..dce06e553c7c 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -40,9 +40,13 @@ 
 #define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
 
 #ifdef CONFIG_KASAN_SW_TAGS
-#define TCR_KASAN_FLAGS TCR_TBI1
+#define TCR_KASAN_SW_FLAGS TCR_TBI1
 #else
-#define TCR_KASAN_FLAGS 0
+#define TCR_KASAN_SW_FLAGS 0
+#endif
+
+#ifdef CONFIG_KASAN_HW_TAGS
+#define TCR_KASAN_HW_FLAGS TCR_TBI1
 #endif
 
 /*
@@ -454,6 +458,9 @@  SYM_FUNC_START(__cpu_setup)
 
 	/* set the TCR_EL1 bits */
 	orr	mte_tcr, mte_tcr, #SYS_TCR_EL1_TCMA1
+#ifdef CONFIG_KASAN_HW_TAGS
+	orr	mte_tcr, mte_tcr, #TCR_KASAN_HW_FLAGS
+#endif
 1:
 #endif
 	msr	mair_el1, x5
@@ -463,7 +470,7 @@  SYM_FUNC_START(__cpu_setup)
 	 */
 	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
 			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
-			TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
+			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS
 #ifdef CONFIG_ARM64_MTE
 	orr	x10, x10, mte_tcr
 	.unreq	mte_tcr