| Message ID | 75637257694de0d4a9e432e1d8270019a4e6328b.1610364681.git.baruch@tkos.co.il (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | gpio: mvebu: Armada 8K/7K PWM support | expand |
On Mon, Jan 11, 2021 at 12:47 PM Baruch Siach <baruch@tkos.co.il> wrote: > > The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) > point to the same counter registers offset. The driver will decide how > to use counters A/B. > > This is different from the convention of pwm on earlier Armada series > (370/38x). On those systems the assignment of A/B counters to GPIO > blocks is coded in both DT and the driver. The actual behaviour of the > current driver on Armada 8K/7K is the same as earlier systems. > > Add also clock properties for base pwm frequency reference. > > Signed-off-by: Baruch Siach <baruch@tkos.co.il> > --- Andrew, Gregory, Sebastian, Can we get your Acks on this patch? Are you fine with it going through the GPIO tree? Bartosz
Hi Baruch, > The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) > point to the same counter registers offset. The driver will decide how > to use counters A/B. > > This is different from the convention of pwm on earlier Armada series > (370/38x). On those systems the assignment of A/B counters to GPIO > blocks is coded in both DT and the driver. The actual behaviour of the > current driver on Armada 8K/7K is the same as earlier systems. > > Add also clock properties for base pwm frequency reference. > > Signed-off-by: Baruch Siach <baruch@tkos.co.il> Applied on mvebu/dt64 Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 +++ > arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > index 12e477f1aeb9..6614472100c2 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > @@ -281,6 +281,9 @@ ap_gpio: gpio@1040 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&ap_pinctrl 0 0 20>; > + marvell,pwm-offset = <0x10c0>; > + #pwm-cells = <2>; > + clocks = <&ap_clk 3>; > }; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > index 994a2fce449a..d774a39334d9 100644 > --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi > @@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, > <85 IRQ_TYPE_LEVEL_HIGH>, > <84 IRQ_TYPE_LEVEL_HIGH>, > <83 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(clk) 1 21>, > + <&CP11X_LABEL(clk) 1 17>; > status = "disabled"; > }; > > @@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; > + marvell,pwm-offset = <0x1f0>; > + #pwm-cells = <2>; > interrupt-controller; > interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, > <81 IRQ_TYPE_LEVEL_HIGH>, > <80 IRQ_TYPE_LEVEL_HIGH>, > <79 IRQ_TYPE_LEVEL_HIGH>; > #interrupt-cells = <2>; > + clock-names = "core", "axi"; > + clocks = <&CP11X_LABEL(clk) 1 21>, > + <&CP11X_LABEL(clk) 1 17>; > status = "disabled"; > }; > }; > -- > 2.29.2 >
Hello Bartosz, > On Mon, Jan 11, 2021 at 12:47 PM Baruch Siach <baruch@tkos.co.il> wrote: >> >> The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) >> point to the same counter registers offset. The driver will decide how >> to use counters A/B. >> >> This is different from the convention of pwm on earlier Armada series >> (370/38x). On those systems the assignment of A/B counters to GPIO >> blocks is coded in both DT and the driver. The actual behaviour of the >> current driver on Armada 8K/7K is the same as earlier systems. >> >> Add also clock properties for base pwm frequency reference. >> >> Signed-off-by: Baruch Siach <baruch@tkos.co.il> >> --- > > Andrew, Gregory, Sebastian, > > Can we get your Acks on this patch? Are you fine with it going through > the GPIO tree? I prefer applying it on our tree to avoid merge conflicts. Gregory > > Bartosz
On Fri, Jan 29, 2021 at 4:56 PM Gregory CLEMENT <gregory.clement@bootlin.com> wrote: > > Hello Bartosz, > > > On Mon, Jan 11, 2021 at 12:47 PM Baruch Siach <baruch@tkos.co.il> wrote: > >> > >> The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) > >> point to the same counter registers offset. The driver will decide how > >> to use counters A/B. > >> > >> This is different from the convention of pwm on earlier Armada series > >> (370/38x). On those systems the assignment of A/B counters to GPIO > >> blocks is coded in both DT and the driver. The actual behaviour of the > >> current driver on Armada 8K/7K is the same as earlier systems. > >> > >> Add also clock properties for base pwm frequency reference. > >> > >> Signed-off-by: Baruch Siach <baruch@tkos.co.il> > >> --- > > > > Andrew, Gregory, Sebastian, > > > > Can we get your Acks on this patch? Are you fine with it going through > > the GPIO tree? > > I prefer applying it on our tree to avoid merge conflicts. > > Gregory Ok, I applied the remaining patches from this series. Bartosz
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 12e477f1aeb9..6614472100c2 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -281,6 +281,9 @@ ap_gpio: gpio@1040 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&ap_pinctrl 0 0 20>; + marvell,pwm-offset = <0x10c0>; + #pwm-cells = <2>; + clocks = <&ap_clk 3>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 994a2fce449a..d774a39334d9 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; + marvell,pwm-offset = <0x1f0>; + #pwm-cells = <2>; interrupt-controller; interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, <85 IRQ_TYPE_LEVEL_HIGH>, <84 IRQ_TYPE_LEVEL_HIGH>, <83 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; + clock-names = "core", "axi"; + clocks = <&CP11X_LABEL(clk) 1 21>, + <&CP11X_LABEL(clk) 1 17>; status = "disabled"; }; @@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; + marvell,pwm-offset = <0x1f0>; + #pwm-cells = <2>; interrupt-controller; interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, <81 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, <79 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; + clock-names = "core", "axi"; + clocks = <&CP11X_LABEL(clk) 1 21>, + <&CP11X_LABEL(clk) 1 17>; status = "disabled"; }; };
The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) point to the same counter registers offset. The driver will decide how to use counters A/B. This is different from the convention of pwm on earlier Armada series (370/38x). On those systems the assignment of A/B counters to GPIO blocks is coded in both DT and the driver. The actual behaviour of the current driver on Armada 8K/7K is the same as earlier systems. Add also clock properties for base pwm frequency reference. Signed-off-by: Baruch Siach <baruch@tkos.co.il> --- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 +++ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++ 2 files changed, 13 insertions(+)