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Thu, 28 Mar 2024 23:15:15 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 28 Mar 2024 23:15:14 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v4 2/6] iommu/arm-smmu-v3: Make arm_smmu_cmdq_init reusable Date: Thu, 28 Mar 2024 23:14:06 -0700 Message-ID: <78032b4ba243d778b1fdc24ea46019da6626a760.1711690673.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|IA0PR12MB8839:EE_ X-MS-Office365-Filtering-Correlation-Id: 7778ef85-e802-456d-e401-08dc4fb7a0bd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2oK+n6MNDLAHZ0BHbX0U7Xm4I4wryyY31ezrOd27saZEhdcq3A6/dO5XS6dpxXSuH2BnEHezNDNhng84F7HJG6uBjU1o8YV9QZnnAx6xA4VWS77ow8syIknTpsssli521TDd+indAUzjjvP8ArkLgtdxTj4eyPQBE+QpLGMgcR+56kuZAOIXNr+HLUXZ6/KtfmcjplJguflUf4A8EPvD2uGZ//M7dmf+niKGRqkD5DVO08s84wQO9N2Ag8MU8eKzFyENz20pfuEGpUGIxhYq3PFKvWm6bCbuAe63Ef8JftIohNOL9KMW6gCsix3l6hDlUSJj/chN8H6v6SYFGanod9vX9MSlnhyjVJBr4ZVX28skZ5dKVuVxwbhq+8TerTzgDnL2NgiaFhLmENUbys86aFcYUdlU6gliaf0eEr/yFcmgMtdSpZQWdrYCxSSHvJrx0d8yIpAlnxI5ChJ5m8Y26pqN5xbuKPcD8LUvK+g7pfVg1VPutONDDukPMdlU5/EKSvH0n1mQB9zDX1n2qemwebBLBqa64YW+NVAtelHbz3eRExx4Qxa4YjPFu3AgToQ5VvYHMCRl3MdPsCtTtEr9dl9nFpc+RjghIafepoLSX8vCIlgigIhP8lu6LZGBKvlGLcNc+zPKj+UZQH1MaY5WF6f9zyydmlhXKYy/ukq958YR77l2XVvJmUKP/x/87fV5f9aIAcKNF/JUvzjidhLjAOgSkYO6Ube1Nmm6KWWuEVMOygC9JGgCs+vUsHKCJSLJ X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(36860700004)(1800799015)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2024 06:15:27.2145 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7778ef85-e802-456d-e401-08dc4fb7a0bd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8839 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240328_231534_133324_917167AC X-CRM114-Status: GOOD ( 13.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension in NVIDIA Tegra241 SoC resues the arm_smmu_cmdq structure while the queue location isn't same as smmu->cmdq. Add a cmdq argument to arm_smmu_cmdq_init() function and shares its define in the header for CMDQV driver to use. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index da3957ad95be..44fcc0c0a149 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3135,9 +3135,9 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, return 0; } -static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) { - struct arm_smmu_cmdq *cmdq = &smmu->cmdq; unsigned int nents = 1 << cmdq->q.llq.max_n_shift; atomic_set(&cmdq->owner_prod, 0); @@ -3162,7 +3162,7 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (ret) return ret; - ret = arm_smmu_cmdq_init(smmu); + ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq); if (ret) return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index b95d9a9ae0a8..4af0976a2338 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -758,6 +758,9 @@ bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd); int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, unsigned long iova, size_t size); +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);