From patchwork Mon Dec 1 22:01:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jungseok Lee X-Patchwork-Id: 5415581 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E03C89F319 for ; Mon, 1 Dec 2014 22:03:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 01C812025A for ; Mon, 1 Dec 2014 22:03:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 142BE2016C for ; Mon, 1 Dec 2014 22:03:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XvZ2I-0005vY-4l; Mon, 01 Dec 2014 22:01:38 +0000 Received: from mail-pd0-x230.google.com ([2607:f8b0:400e:c02::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XvZ2E-0005qx-Lx for linux-arm-kernel@lists.infradead.org; Mon, 01 Dec 2014 22:01:35 +0000 Received: by mail-pd0-f176.google.com with SMTP id y10so11688203pdj.35 for ; Mon, 01 Dec 2014 14:01:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:content-type:content-transfer-encoding:subject:date:message-id :cc:to:mime-version; bh=aWqgusGmaLuet1DCTecWybqY+ZOJKN0OpbRYSN2rKlg=; b=Rf2ZVV43v74yvvpllDhmJ98ieEH9TNcZ2iC1GLPnqCSSZBtoo6QR16tSHPxdC8lUCu Ym7MVUTsQVCyIxaJFEIyXpSfNmhLuXr5RtQLiGWLLT53Zw2O+4oe1yCXqNLQQsnVHUEy lI21+xRvXuAi8OofwYgnfqhf8Szm8d4K0s/dhCpd0b4gSNzldgzNARH+qvddH6YN9DP+ NY79ABQXhh+arSijt5CQmU0E819x0S80IUSyxroYAbLJPd/iFPArC6V+3nVYYT96eyOr gjb+uRUOKbjPwc10WLUEkJo3aeK88MmtwFFYHQgRHbaZGtEPsXmhANogcTrjKSWp7Be7 EX7g== X-Received: by 10.69.31.138 with SMTP id km10mr21992pbd.6.1417471271747; Mon, 01 Dec 2014 14:01:11 -0800 (PST) Received: from [192.168.123.132] ([182.215.209.43]) by mx.google.com with ESMTPSA id gz10sm18521400pac.23.2014.12.01.14.01.09 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 01 Dec 2014 14:01:11 -0800 (PST) From: Jungseok Lee Subject: [PATCH] arm64: Implement support for read-mostly sections Date: Tue, 2 Dec 2014 07:01:06 +0900 Message-Id: <7F4979C9-A608-4641-B2DD-0A09FBCCC4A0@gmail.com> To: linux-arm-kernel@lists.infradead.org Mime-Version: 1.0 (Apple Message framework v1283) X-Mailer: Apple Mail (2.1283) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141201_140134_738209_D306EB36 X-CRM114-Status: GOOD ( 12.41 ) X-Spam-Score: -0.6 (/) Cc: Catalin Marinas , Will Deacon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi All, I'm not fully understand why this code is missed in ARM64, so my analysis below might be wrong. Best Regards Jungseok Lee ---->8---- As putting data which is read mostly together, we can avoid unnecessary cache line bouncing. Other architectures, such as ARM and x86, adopted the same idea. Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Jungseok Lee Acked-by: Catalin Marinas --- arch/arm64/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 88cc05b..c1a2a9f 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -30,6 +30,8 @@ */ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) + #ifndef __ASSEMBLY__ static inline int cache_line_size(void)