| Message ID | 7b69c9752713ce22f04688e83ec78f8aa67c63dc.1589558615.git.saiprakash.ranjan@codeaurora.org (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 7f1a1c2c57dbda7278ef06700efcac63433b9893 |
| Headers | show |
| Series | coresight: etm4x: Add support to skip trace unit power up | expand |
On Fri, 15 May 2020 at 10:23, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> wrote: > > From: Tingwei Zhang <tingwei@codeaurora.org> > > Add "qcom,skip-power-up" property to identify systems which can > skip powering up of trace unit since they share the same power > domain as their CPU core. This is required to identify such > systems with hardware errata which stops the CPU watchdog counter > when the power up bit is set (TRCPDCR.PU). > > Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org> > Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index 846f6daae71b..e4b2eda0b53b 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -108,6 +108,13 @@ its hardware characteristcs. > * arm,cp14: must be present if the system accesses ETM/PTM management > registers via co-processor 14. > > + * qcom,skip-power-up: boolean. Indicates that an implementation can > + skip powering up the trace unit. TRCPDCR.PU does not have to be set > + on Qualcomm Technologies Inc. systems since ETMs are in the same power > + domain as their CPU cores. This property is required to identify such > + systems with hardware errata where the CPU watchdog counter is stopped > + when TRCPDCR.PU is set. > + > * Optional property for TMC: Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > > * arm,buffer-size: size of contiguous buffer space for TMC ETR > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation
On Fri, 15 May 2020 21:52:33 +0530, Sai Prakash Ranjan wrote: > From: Tingwei Zhang <tingwei@codeaurora.org> > > Add "qcom,skip-power-up" property to identify systems which can > skip powering up of trace unit since they share the same power > domain as their CPU core. This is required to identify such > systems with hardware errata which stops the CPU watchdog counter > when the power up bit is set (TRCPDCR.PU). > > Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org> > Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++ > 1 file changed, 7 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 846f6daae71b..e4b2eda0b53b 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -108,6 +108,13 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. + * qcom,skip-power-up: boolean. Indicates that an implementation can + skip powering up the trace unit. TRCPDCR.PU does not have to be set + on Qualcomm Technologies Inc. systems since ETMs are in the same power + domain as their CPU cores. This property is required to identify such + systems with hardware errata where the CPU watchdog counter is stopped + when TRCPDCR.PU is set. + * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR