@@ -47,6 +47,13 @@ aliases {
ethernet0 = &avb0;
};
+ can_transceiver0: can-phy0 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ max-bitrate = <5000000>;
+ };
+
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
@@ -174,6 +181,25 @@ phy0: ethernet-phy@0 {
};
};
+&can_clk {
+ clock-frequency = <40000000>;
+};
+
+&canfd {
+ pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ phys = <&can_transceiver0>;
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
&extal_clk {
clock-frequency = <16666666>;
};
@@ -305,6 +331,21 @@ pins_mii {
};
};
+ can_clk_pins: can-clk {
+ groups = "can_clk";
+ function = "can_clk";
+ };
+
+ canfd0_pins: canfd0 {
+ groups = "canfd0_data";
+ function = "canfd0";
+ };
+
+ canfd1_pins: canfd1 {
+ groups = "canfd1_data";
+ function = "canfd1";
+ };
+
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
Enable confirmed-working CAN-FD channels 0 and 1 on the Gray Hawk Single development board: - Channel 0 uses an NXP TJR1443AT CAN transceiver, which must be enabled through a GPIO, - Channels 1-3 use Microchip MCP2558FD-H/SN CAN transceivers, which do not need explicit description, but channels 2-3 do not seem to work. Inspired by a patch for Gray Hawk in the BSP by Duy Nguyen. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - Add missing pinctrl-names, - Correct TJR1443AT Enable GPIO, - Reword now channels 0 and 1 work. Changes compared to the BSP: - Add can_clk, - Add missing can_transceiver0, - Keep channels 2 and 3 disabled, - Preserve sort order. --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+)