@@ -841,6 +841,87 @@ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
};
};
+&lcdif {
+ status = "okay";
+
+ port@0 {
+ lcdif_dpi_out: endpoint {
+ remote-endpoint = <&dpi_mux_from_lcdif>;
+ };
+ };
+};
+
+&iomuxc_gpr {
+ mipi_mux: mipi-mux {
+ compatible = "mux-input-bridge";
+ mux-controls = <&mux 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpi_mux_from_lcdif: endpoint {
+ remote-endpoint = <&lcdif_dpi_out>;
+ };
+ };
+
+ port@1 { /* dcss */
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ dpi_mux_out: endpoint {
+ remote-endpoint = <&nwl_dpi_in>;
+ };
+
+ };
+ };
+ };
+};
+
+&mipi_dsi {
+ status = "okay";
+ panel@0 {
+ compatible = "rocktech,jh057n00900";
+ reg = <0>;
+ backlight = <&backlight_dsi>;
+ reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_2v8_p>;
+ iovcc-supply = <®_1v8_p>;
+ port@0 {
+ panel_in: endpoint {
+ remote-endpoint = <&nwl_dsi_out>;
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ nwl_dpi_in: endpoint {
+ remote-endpoint = <&dpi_mux_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ nwl_dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
&pgc_gpu {
power-supply = <&buck3_reg>;
};
Enable MIPI LCD panel output by adding nodes for the NWL DSI host controller, the mux-input-bridge, the Rocktech panel and the eLCDIF display controller. Signed-off-by: Guido Günther <agx@sigxcpu.org> --- .../dts/freescale/imx8mq-librem5-devkit.dts | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+)